URI | http://purl.tuc.gr/dl/dias/BC1F20E3-5B3A-46AD-8C3D-9FB6720D557D | - |
Identifier | http://users.isc.tuc.gr/~kpapadimitriou/publications/EvalPreloadPR-fpl2006.pdf | - |
Language | en | - |
Extent | 4 pages | en |
Title | Performance evaluation of a preloading model in dynamically reconfigurable processors | en |
Creator | Papadimitriou Kyprianos | en |
Creator | Παπαδημητριου Κυπριανος | el |
Creator | Dollas Apostolos | en |
Creator | Δολλας Αποστολος | el |
Publisher | Institute of Electrical and Electronics Engineers | en |
Content Summary | Dynamic reconfiguration allows for the reuse of the same
hardware by different tasks of an application at different
stages of its execution. However, reconfiguring the hardware
at run-time incurs a configuration delay causing performance
degradation of the application. This paper evaluates
a preloading model that hides the configuration overhead.
An existing preloading model is augmented according
to the physical constraints of the system. A reduction of 6%
up to 86% in execution time has been obtained with the new
model. | en |
Type of Item | Πλήρης Δημοσίευση σε Συνέδριο | el |
Type of Item | Conference Full Paper | en |
License | http://creativecommons.org/licenses/by/4.0/ | en |
Date of Item | 2015-11-12 | - |
Date of Publication | 2006 | - |
Subject | Automatic computers | en |
Subject | Automatic data processors | en |
Subject | Computer hardware | en |
Subject | Computing machines (Computers) | en |
Subject | Electronic brains | en |
Subject | Electronic calculating-machines | en |
Subject | Electronic computers | en |
Subject | Hardware, Computer | en |
Subject | computers | en |
Subject | automatic computers | en |
Subject | automatic data processors | en |
Subject | computer hardware | en |
Subject | computing machines computers | en |
Subject | electronic brains | en |
Subject | electronic calculating machines | en |
Subject | electronic computers | en |
Subject | hardware computer | en |
Bibliographic Citation | K. Papadimitriou and A. Dollas, "Performance evaluation of a preloading model in dynamically reconfigurable processors," in IEEE International Conference on Field Programmable Logic and Aplications, 2006, pp. 901-904. | en |