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A reconfigurable logic-based processor for the SCAN image and video encryption algorithm

Dollas Apostolos, Bourbakis, Nikolaos G, Kachris, Christoforos

Πλήρης Εγγραφή


URI: http://purl.tuc.gr/dl/dias/8C5ACDDD-0A6E-4CCB-8599-731E4A04FAEE
Έτος 2003
Τύπος Δημοσίευση σε Περιοδικό με Κριτές
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Λεπτομέρειες
Βιβλιογραφική Αναφορά C. Kachris, N. Bourbakis and A. Dollas, "A reconfigurable logic-based processor for the SCAN image and video encryption algorithm," Int. J. Parall. Programm., vol. 31, no. 6, pp. 489-506, Dec. 2003. doi:10.1023/B:IJPP.0000004512.53221.ff https://doi.org/10.1023/B:IJPP.0000004512.53221.ff
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Περίληψη

This paper presents a detailed architecture and a reconfigurable logic based hardware design of the SCAN algorithm. This architecture can be used to encrypt high resolution images in real-time. Although the SCAN algorithm is a block cipher algorithm with arbitrarily large blocks, the present design is for 64×64 pixel blocks in order to provide real-time image encryption throughput. The architecture was initially targeted at the Xilinx XCV-1000 FPGA, for which design and performance results are presented in the paper.

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