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Hayashi-Yoshida coefficient estimator implementation in CUDA

Fotopoulos Spyridon

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Year 2017
Type of Item Diploma Work
Bibliographic Citation Spyridon Fotopoulos, "Hayashi-Yoshida coefficient estimator implementation in CUDA", Diploma Work, School of Electronic Computer Engineering, Technical University of Crete, Chania, Greece, 2017
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The increased need for fast computational systems that can process large streaming inputs in real-time, combined with the limits in parallelism of the CPU's and the difficulties of FPGA based designs have led the hardware community in the search for alternatives. In this diploma thesis, we present a design that leverages the vast parallel capabilities of current GPU's that contain thousands of cores. We implement on a CUDA-enabled GPU two designs of the Hayashi-Yoshida correlation coefficient estimator algorithm, with and without window, for large inputs and we can yield an impressive fifteen-fold and twenty-fold decrease in overall computing latency respectively, coupled with the ability to handle simultaneously up to 18000 inputs.

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