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Technical University of Crete
Technical University of Crete
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| URI: | http://purl.tuc.gr/dl/dias/AA9BF518-0108-4F87-A6A7-5A488FBC7B25 | ||
| Year | 2018 | ||
| Type of Item | Diploma Work | ||
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| Bibliographic Citation | Georgios Pekridis, "Implementation of ARM processor by using Bluespec language", Diploma Work, School of Electrical and Computer Engineering, Technical University of Crete, Chania, Greece, 2018 https://doi.org/10.26233/heallink.tuc.71171 | ||
| Appears in Collections |
The goal of this thesis was to construct an ARM processor using the Bluspec System Verilog language(BSV). BSV has a fundamentally different approach to hardware design, comparing to other Hardware Description Languages. It is based on circuit generation rather than merely circuit description and is also based on atomic transactional rules instead of a globally synchronous view of the world. The processor belongs to the ARM7 family, it has a 3-stage pipeline, it uses a 32-bit architecture and is based on ARMv4 instruction set. In addition the processor supports all the operating modes. The modes of operation are User, Fast Interrupt(FIQ), Interrupt(IRQ), Supervisor, Abort, System and Undefined. The amount of different types of instructions that were implemented is 26. Each and every one of these types has additional functions depending on the condition codes and the addressing modes of the instruction. For the verification of the design, assembly code was used. This assembly code was produced by C++ code, through the ARM GCC.
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