Ιδρυματικό Αποθετήριο
Πολυτεχνείο Κρήτης
Πολυτεχνείο Κρήτης
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| URI | http://purl.tuc.gr/dl/dias/08D76F80-8D25-43A2-9BA5-0199300A8623 | - |
| Αναγνωριστικό | http://ebooks.iospress.nl/publication/42695 | - |
| Αναγνωριστικό | https://doi.org/10.3233/978-1-61499-621-7-553 | - |
| Γλώσσα | en | - |
| Μέγεθος | 10 pages | en |
| Τίτλος | A run-time system for partially reconfigurable FPGAs: The case of STMicroelectronics SPEAr board | en |
| Δημιουργός | Charitopoulos Georgios | en |
| Δημιουργός | Χαριτοπουλος Γεωργιος | el |
| Δημιουργός | Pnevmatikatos Dionysios | en |
| Δημιουργός | Πνευματικατος Διονυσιος | el |
| Δημιουργός | Santambrogio, Marco | en |
| Δημιουργός | Papadimitriou Kyprianos | en |
| Δημιουργός | Παπαδημητριου Κυπριανος | el |
| Δημιουργός | Pau Danillo | en |
| Εκδότης | Elsevier | en |
| Περίληψη | During recent years much research focused on making Partial Reconfiguration (PR) more widespread. The FASTER project aimed at realizing an integrated toolchain that assists the designer in the steps of the design flow that are necessary to port a given application onto an FPGA device. The novelty of the framework lies in the use of partial dynamic reconfiguration seen as a first class citizen throughout the entire design flow in order to exploit FPGA device potential. The STMicroelectronics SPEAr development platform combines an ARM processor alongside with a Virtex-5 FPGA daughter-board. While partial reconfiguration in the attached board was considered as feasible from the beginning, there was no full implementation of a hardware architecture using PR. This work describes our efforts to exploit PR on the SPEAr prototyping embedded platform. The paper discusses the implemented architecture, as well as the integration of Run-Time System Manager for scheduling (run-time reconfiogurable) hardware and software tasks.We also propose improvements that can be exploited in order to make the PR utility more easy-to-use on future projects on the SPEAr platform. | en |
| Τύπος | Peer-Reviewed Journal Publication | en |
| Τύπος | Δημοσίευση σε Περιοδικό με Κριτές | el |
| Άδεια Χρήσης | http://creativecommons.org/licenses/by/4.0/ | en |
| Ημερομηνία | 2018-11-19 | - |
| Ημερομηνία Δημοσίευσης | 2016 | - |
| Θεματική Κατηγορία | FPGA | en |
| Θεματική Κατηγορία | Partial reconfiguration | en |
| Θεματική Κατηγορία | Run-time system manager | en |
| Βιβλιογραφική Αναφορά | G. Charitopoulos, D. Pnevmatikatos, M. D. Santambrogio, K. Papadimitriou and D. Pau, "A run-time system for partially reconfigurable FPGAs: the case of STMicroelectronics SPEAr board," Adv. Par. Com., vol. 27, pp. 553-562, 2016. doi: 10.3233/978-1-61499-621-7-553 | en |
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