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Technical University of Crete
Technical University of Crete
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| URI | http://purl.tuc.gr/dl/dias/15E40951-8CD8-4825-9637-7B98DEF113C4 | - |
| Identifier | https://doi.org/10.1109/ESSDERC.2019.8901775 | - |
| Identifier | https://ieeexplore.ieee.org/abstract/document/8901775 | - |
| Language | en | - |
| Extent | 4 pages | en |
| Title | Compact modeling of low frequency noise and thermal noise in junction field effect transistors | en |
| Creator | Makris Nikolaos | en |
| Creator | Μακρης Νικολαος | el |
| Creator | Chevas Loukas | en |
| Creator | Χεβας Λουκας | el |
| Creator | Bucher Matthias | en |
| Creator | Bucher Matthias | el |
| Publisher | Institute of Electrical and Electronics Engineers | en |
| Content Summary | This paper presents a novel charge-based approach to modeling bias-dependent noise in junction field-effect transistors (JFETs). Low frequency noise as well as thermal noise aspects are modeled within the recent charge-based model of the double-gate (DG) JFET. For low frequency noise, mobility fluctuations according to the Hooge model is addressed. Thermal noise is expressed within the charge-based modeling approach. The models are validated with respect to TCAD simulations and show correct dependence over a range of gate and drain bias. A custom setup for low frequency noise measurement of JFETs is described. Noise measurements of n-JFETs are discussed, and the compact model is compared with the measurement. | en |
| Type of Item | Πλήρης Δημοσίευση σε Συνέδριο | el |
| Type of Item | Conference Full Paper | en |
| License | http://creativecommons.org/licenses/by/4.0/ | en |
| Date of Item | 2020-04-23 | - |
| Date of Publication | 2019 | - |
| Subject | Compact model | en |
| Subject | JFET | en |
| Subject | Junction field effect transistor | en |
| Subject | Low frequency noise | en |
| Subject | Semiconductor device measurement | en |
| Subject | Thermal noise | en |
| Bibliographic Citation | N. Makris, L. Chevas and M. Bucher, "Compact modeling of low frequency noise and thermal noise in junction field effect transistors," in 49th European Solid-State Device Research Conference, 2019, pp. 198-201. doi: 10.1109/ESSDERC.2019.8901775 | en |
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