Full system architectural simulation on the HARP integrated CPU-FPGA platformFull system architectural simulation on the HARP integrated CPU-FPGA platformΠλήρης αρχιτεκτονική προσομοίωση στην ενσωματωμένη CPU-FPGA πλατφόρμα HARP
Μεταπτυχιακή Διατριβή
Master Thesis
2019-08-192019enSimulation is vital when developing novel software or hardware systems. Cycle accurate architectural simulators are extremely important tools for verifying experimental hardware platforms, system profiling, and advanced software development. Their main disadvantage is limited throughput when simulating large systems with multiple processing units and peripherals.
This Master’s thesis describes the development process of a series of HW components for Intel’s HARP CPU-FPGA hybrid platform, that will be used to synthesize a Trace-Driven FPGAAccelerated Full-System Architectural Simulator. Essential development steps and protocols, that are required to incorporate accelerators on the HARP platform, are also highlighted. The developed
modules, facilitate high-performance HW components that can accurately and efficiently simulate a highly configurable L1 Cache and 3 highly configurable Branch Predictor HW structures.
Optimal performance for the proposed HW simulator can be achieved when executed in coordination with a fast functional simulator running on SW. A state of the art API exports trace-data from the functional simulation at run time, in order to load the HW modules. Using these data, the HW modules can accurately and efficiently execute architectural simulation. Apart from simulation results and timing statistics, the models can generate the system’s state at different timestamps, depending on the executed traces. These architectural checkpoints can later be used to either validate the functionality of the components, determine the overall system’s behavior using the sampling technique, execute new architectural simulations, or to warm-up other full system simulations.http://creativecommons.org/licenses/by/4.0/Πολυτεχνείο Κρήτης::Σχολή Ηλεκτρολόγων Μηχανικών και Μηχανικών ΥπολογιστώνKyriakidis_Konstantinos_MSc_2019.pdfChania [Greece]Library of TUC2019-08-06application/pdf6.1 MBfree
Kyriakidis Konstantinos
Κυριακιδης Κωνσταντινος
Pnevmatikatos Dionysios
Πνευματικατος Διονυσιος
Dollas Apostolos
Δολλας Αποστολος
Papaefstathiou Ioannis
Παπαευσταθιου Ιωαννης
Πολυτεχνείο Κρήτης
Technical University of Crete
HARP platform
Hardware architecture
Architectural simulation
Trace-Driven
Sampling
Hybrid platform
CCI-P
System-States
OPAE
HARP
AFU
ASE
FIU
HW
SW
BPs
API