Total ionizing dose effects on analog performance of 65 nm bulk CMOS with enclosed-gate and standard layoutTotal ionizing dose effects on analog performance of 65 nm bulk CMOS with enclosed-gate and standard layout
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2019-09-062018enHigh doses of ionizing irradiation cause significant shifts in design parameters of standard bulk silicon CMOS. Analog performance of a commercial 65 nm CMOS technology is examined for standard and enclosed gate layouts, with Total Ionizing Dose (TID) up to 500 Mrad(SiO2). The paper provides insight into geometrical and bias dependence of key design parameters such as threshold voltage, DIBL, transconductance efficiency, slope factor, and intrinsic gain. A modeling approach for an efficient representation of saturation transfer characteristics under TID from weak through moderate and strong inversion and over channel length is discussed.http://creativecommons.org/licenses/by/4.0/166-170IEEE International Conference on Microelectronic Test Structures
Bucher Matthias
Bucher Matthias
Nikolaou Aristeidis
Νικολαου Αριστειδης
Papadopoulou Alexia
Παπαδοπουλου Αλεξια
Makris Nikolaos
Μακρης Νικολαος
Chevas Loukas
Χεβας Λουκας
Borghello Giulio
Koch Henri D.
Faccio Federico
Institute of Electrical and Electronics Engineers
Analog parameters
Enclosed layout
Modeling
MOSFET
Parameter extraction
Radiation hardness
Total ionizing dose