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 7996-8010 out of 18412 results
7996 I. Papaefstathiou. (2000,May). A complete framework for on-line Compression of ATM streams. Presented at IEEE/IEE International Conference on Telecommunications 2000. [Online]. Available: http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.20.344&rep=rep1&type=pdf2015-11-16
7997 Z. Agioutantis, S. Maurigiannakis and C. Stiakakis, "Modeling the uniaxial compression test in rocks: Comparison of different approaches", in Proceedings of the 4th GRACM Congress On Computational Mechanics, 2002.2015-11-16
7998 C. Tsoutrelis, S. Maurigiannakis and V. Roumpos, "Effectiveness of the Swellex rockreinforcement system in the Madem Lakkos and Olympias mines," presented at 3rd National Congress of Mineral Wealth, 2000.2015-11-16
7999 I. Papaefstathiou, "Accelerating ATM: on-line compression of ATM streams," in 18th IEEE International Performance, Computing, and Communications Conference, 1999, pp. 233 - 239. doi: 10.1109/PCCC.1999.7494432015-11-16
8000 I. Papaefstathiou, "Compressing ATM streams on-line," in 1999 IEEE Data Compression Conference, 1999. doi: 10.1109/DCC.1999.7857002015-11-16
8001 A. Brown, D. Chian, N. Mehta, I. Papaefstathiou, J. Simer, T. Blackwell, M. Smith, W. Yang. (1997,June). Using MML to Simulate Multiple Dual-Ported SRAMs: Parallel Routing Lookups in an ATM Switch Controller. Presented at Workshop on Mixing Logic and DRAM, International Symposium of Computer Architecture. [Online]. Available: http://www.126doc.com/p-4098460.html2015-11-16
8002 I. Papaefstathiou, A. Brown, J. Simer, D. Sobel, J. Sutaria, Y. WangT. Blackwell, M. Smith, W. Yang, "An IRAM-based architecture for a single-chip ATM switch," in 6th IEEE International Conference on Electronics, Circuits and Systems, 1999, pp. 97 - 100. doi: 10.1109/ICECS.1999.8122322015-11-16
8003 I. Papaefstathiou, G. Kornaros, N. Zervos, "Software processing performance in network processors," in IEEE Design Automation and Test in Europe, 2004, pp. 186 - 191. doi: 10.1109/DATE.2004.12692282015-11-16
8004 T. Orphanoudakis, G. Kornaros, H. Leligou, I. Papaefstathiou, S. Perissakis, N. Zervos. (2003,May). Scheduling components for multi-gigabit network SoCs. Presented at 2003 SPIE First International Symposium on Microtechnologies for the New Millennium. [Online]. Available: http://users.uop.gr/~fanis/html_files/pdf_files/papers/Conferences/C16_spie03_NPUsched.pdf2015-11-16
8005 G. Kornaros, I. Papaefstathiou, A. Nikologiannis, N. Zervos, "A fully programmable memory management system optimizing queue handling at multi gigabit rates," in 40th IEEE/ACM Design Automation Conference , 2003, pp. 54 - 59. doi: 10.1109/DAC.2003.12188002015-11-16
8006 N. Mouratidis, G. Lykakis, A. Tavoularis, A. Kostopoulos, F. Petreas, D. Economou, A. Manousaridis, V. Vlaggoulis, I. Papaefstathiou, C. Georgopoulos, G. Konstantoulakis, "Convergence Processor: Standard and Custom IP in an Innovative SoC Design for Broadband Residential Applications," presented at IIIS International Conference on Computer, Communication and Control Technologies, 2003.2015-11-16
8007 I. Papaefstathiou, H. Leligou, T. Orphanoudakis, G. Kornaros, N. Zervos, G. Konstantoulakis, "An innovative scheduling scheme for high-speed network processors," in IEEE International Symposium on Circuits and Systems, 2003, pp. II-93 - II-96. doi: 10.1109/ISCAS.2003.12058992015-11-16
8008 G. Kornaros, T. Orphanoudakis, I. Papaefstathiou, "GFS: an efficient implementation of fair scheduling for multigigabit packet networks," in 14th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2003), 2003, pp. 389 - 399. doi: 10.1109/ASAP.2003.12128622015-11-16
8009 I. Papaefstathiou, C. Sotiriou. (2002,May). Read, Use, Simulate, Experiment and Build : An Integrated Approach for Teaching Computer Architecture. Presented at 8th Workshop on Computer Architecture Education (WCAE 2002), 29th International Symposium on Computer Architecture (ISCA 2002). [Online]. Available: https://www.ncsu.edu/wcae/ISCA2002/submissions/papaefstathiou.pdf2015-11-16
8010 I. Papaefstathiou, "An ultra high-speed compressor for packet networks," in 8th IEEE International Conference on Electronics, Circuits and Systems, 2001, pp. 1259 - 1263. doi: 10.1109/ICECS.2001.9574442015-11-16
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