Σχολή Ηλεκτρολόγων Μηχανικών και Μηχανικών Υπολογιστών

Μέχρι και τον Ιούνιο του 2016, η Σχολή Ηλεκτρολόγων Μηχανικών και Μηχανικών Υπολογιστών ονομαζόταν Σχολή Ηλεκτρονικών Μηχανικών και Μηχανικών Υπολογιστών.

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Τελευταίες Υποβολές

	1726-1740 από 4097 αποτελέσματα
1726	P. Mattheakis, I. Papaefstathiou, "Significantly reducing MPI intercommunication latency and power overhead in both embedded and HPC systems," ACM Transactions on Architecture and Code Optimization, vol. 9, no. 4., Jan., 2013. doi: 10.1145/2400682.2400710	2015-11-16
1727	E. Ovcin, C. Cerato, D. Smith and N. Moumoutzis, "pSkills: insegnare informatica con i moderni linguaggi di programmazione educativi", in DIDAMATICA 2011, 4-6 Maggio 2011.	2015-11-16
1728	M. Christoulakis, A. Pitsiladis, A. Moraiti, N. Moumoutzis and S. Christodoulakis, "EShadow A Tool for Digital Storytelling Based on Traditional Greek Shadow Theatre", in 1st International Workshop on Intelligent Digital Games for Empowerment and Inclusion on Foundations of Digital Games Conference, 2013.	2015-11-16
1729	I. Mavroidis, D. Mavroidis, I. Papaefstathiou, "Accelerating Emulation and Providing Full Chip Observability and Controllability," IEEE Design and Test, vol. 26, no. 6, pp. 84-94, Nov./Dec. 2009. doi: 10.1109/MDT.2009.136	2015-11-16
1730	G. Mplemenos, K. Papadopoulos, I. Papaefstathiou, "Using Reconfigurable Hardware Devices in WSNs for Reducing the Energy Consumption of Routing and Security Tasks," in IEEE Global Telecommunications Conference, 2010, pp. 1-5. doi: 10.1109/GLOCOM.2010.5683605	2015-11-16
1731	D. Simos, I. Papaefstathiou, M. Katevenis, "Towards Fabric-On-a-chip(FoC) : A 400Gbps 32×32 Variable-Packet-Size Buffered Crossbar (CICQ) Single-Chip Switch Core," IEEE Design and Test, to be published.	2015-11-16
1732	I. Papaefstathiou, C. Manifavas. (2014). Evaluation of Micropayment Transaction Cost. Journal of Electronic Commerce Research.[Online]. Available: http://web.csulb.edu/journals/jecr/issues/20042/Paper3.pdf	2015-11-16
1733	I. Papaefstathiou, A. Nikologiannis, B. Doshi, E. Grosse. (2004,Sept/Oct). Network Processors for Future High-End Systems and Applications. IEEE Micro. [Online]. Available: https://www.computer.org/csdl/mags/mi/2004/05/m5007.pdf	2015-11-16
1734	I. Papaefstathiou, S. Perissakis, T. Orphanoudakis, N. Nikolaou, G. Kornaros, D. Pnevmatikatos, G. Konstantoulakis, N. Zervos, "PR03: a hybrid NPU architecture," IEEE Micro, vol. 24, no. 5, pp. 20 - 33, March, 2004. doi: 10.1109/MM.2004.55	2015-11-16
1735	I. Papaefstathiou, K. Vlachos, V. Nikolaou, W. Lawrence, " Packet processing acceleration with a 3-stage re-configurable pipeline engine," IEEE Communications Letters, vol. 8, no. 3, Mar., 2004.	2015-11-16
1736	I. Papaefstathiou, " Low-level Hardware Compression for Multi-Gigabit Networks," Journal of Circuits, Systems and Computers, vol. 13, no. 6, pp. 1307-1319, Dec. 2004. doi: 10.1142/S0218126604001969	2015-11-16
1737	I. Papaefstathiou, "Titan II: an IPComp processor for 10Gbit/sec networks," IEEE Design and Test (DandT)., pp. 234 - 235, Nov. 2004. doi:10.1109/ISVLSI.2003.1183479	2015-11-16
1738	I. Papaefstathiou, V. Papaefstathiou, C. Sotiriou, "Elsevier Journal on Microprocessors and Microsystems," vol. 28, no. 10, pp. 561-571, Sept. 2013. doi:10.1016/j.micpro.2004.08.009	2015-11-16
1739	I. Papaefstathiou. (2000,May). A complete framework for on-line Compression of ATM streams. Presented at IEEE/IEE International Conference on Telecommunications 2000. [Online]. Available: http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.20.344&rep=rep1&type=pdf	2015-11-16
1740	I. Papaefstathiou, "Accelerating ATM: on-line compression of ATM streams," in 18th IEEE International Performance, Computing, and Communications Conference, 1999, pp. 233 - 239. doi: 10.1109/PCCC.1999.749443	2015-11-16
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