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Μέχρι και τον Ιούνιο του 2016, η Σχολή Ηλεκτρολόγων Μηχανικών και Μηχανικών Υπολογιστών ονομαζόταν Σχολή Ηλεκτρονικών Μηχανικών και Μηχανικών Υπολογιστών.

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 2041-2055 από 4410 αποτελέσματα
2041 M. Christoulakis, A. Pitsiladis, A. Moraiti, N. Moumoutzis and S. Christodoulakis, "EShadow A Tool for Digital Storytelling Based on Traditional Greek Shadow Theatre", in 1st International Workshop on Intelligent Digital Games for Empowerment and Inclusion on Foundations of Digital Games Conference, 2013. 2015-11-16
2042 I. Mavroidis, D. Mavroidis, I. Papaefstathiou, "Accelerating Emulation and Providing Full Chip Observability and Controllability," IEEE Design and Test, vol. 26, no. 6, pp. 84-94, Nov./Dec. 2009. doi: 10.1109/MDT.2009.1362015-11-16
2043 G. Mplemenos, K. Papadopoulos, I. Papaefstathiou, "Using Reconfigurable Hardware Devices in WSNs for Reducing the Energy Consumption of Routing and Security Tasks," in IEEE Global Telecommunications Conference, 2010, pp. 1-5. doi: 10.1109/GLOCOM.2010.56836052015-11-16
2044 D. Simos, I. Papaefstathiou, M. Katevenis, "Towards Fabric-On-a-chip(FoC) : A 400Gbps 32×32 Variable-Packet-Size Buffered Crossbar (CICQ) Single-Chip Switch Core," IEEE Design and Test, to be published.2015-11-16
2045 I. Papaefstathiou, C. Manifavas. (2014). Evaluation of Micropayment Transaction Cost. Journal of Electronic Commerce Research.[Online]. Available: http://web.csulb.edu/journals/jecr/issues/20042/Paper3.pdf2015-11-16
2046 I. Papaefstathiou, A. Nikologiannis, B. Doshi, E. Grosse. (2004,Sept/Oct). Network Processors for Future High-End Systems and Applications. IEEE Micro. [Online]. Available: https://www.computer.org/csdl/mags/mi/2004/05/m5007.pdf2015-11-16
2047 I. Papaefstathiou, S. Perissakis, T. Orphanoudakis, N. Nikolaou, G. Kornaros, D. Pnevmatikatos, G. Konstantoulakis, N. Zervos, "PR03: a hybrid NPU architecture," IEEE Micro, vol. 24, no. 5, pp. 20 - 33, March, 2004. doi: 10.1109/MM.2004.552015-11-16
2048 I. Papaefstathiou, K. Vlachos, V. Nikolaou, W. Lawrence, " Packet processing acceleration with a 3-stage re-configurable pipeline engine," IEEE Communications Letters, vol. 8, no. 3, Mar., 2004.2015-11-16
2049 I. Papaefstathiou, " Low-level Hardware Compression for Multi-Gigabit Networks," Journal of Circuits, Systems and Computers, vol. 13, no. 6, pp. 1307-1319, Dec. 2004. doi: 10.1142/S02181266040019692015-11-16
2050 I. Papaefstathiou, "Titan II: an IPComp processor for 10Gbit/sec networks," IEEE Design and Test (DandT)., pp. 234 - 235, Nov. 2004. doi:10.1109/ISVLSI.2003.11834792015-11-16
2051 I. Papaefstathiou, V. Papaefstathiou, C. Sotiriou, "Elsevier Journal on Microprocessors and Microsystems," vol. 28, no. 10, pp. 561-571, Sept. 2013. doi:10.1016/j.micpro.2004.08.0092015-11-16
2052 I. Papaefstathiou. (2000,May). A complete framework for on-line Compression of ATM streams. Presented at IEEE/IEE International Conference on Telecommunications 2000. [Online]. Available: http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.20.344&rep=rep1&type=pdf2015-11-16
2053 I. Papaefstathiou, "Accelerating ATM: on-line compression of ATM streams," in 18th IEEE International Performance, Computing, and Communications Conference, 1999, pp. 233 - 239. doi: 10.1109/PCCC.1999.7494432015-11-16
2054 I. Papaefstathiou, "Compressing ATM streams on-line," in 1999 IEEE Data Compression Conference, 1999. doi: 10.1109/DCC.1999.7857002015-11-16
2055 A. Brown, D. Chian, N. Mehta, I. Papaefstathiou, J. Simer, T. Blackwell, M. Smith, W. Yang. (1997,June). Using MML to Simulate Multiple Dual-Ported SRAMs: Parallel Routing Lookups in an ATM Switch Controller. Presented at Workshop on Mixing Logic and DRAM, International Symposium of Computer Architecture. [Online]. Available: http://www.126doc.com/p-4098460.html2015-11-16
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