Institutional Repository
Technical University of Crete
Technical University of Crete
EN
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EL
| URI | http://purl.tuc.gr/dl/dias/58F95797-B712-4999-9DDE-F2FC5A8CB56C | - |
| Identifier | https://doi.org/10.26233/heallink.tuc.17741 | - |
| Language | en | - |
| Extent | 60 pages | en |
| Title | Reliable runtime architecture for multiprocessor systems on chip | en |
| Creator | Skarlatos Dimitrios | en |
| Creator | Σκαρλατος Δημητριος | el |
| Contributor [Thesis Supervisor] | Pnevmatikatos Dionysios | en |
| Contributor [Thesis Supervisor] | Πνευματικατος Διονυσιος | el |
| Contributor [Committee Member] | Dollas Apostolos | en |
| Contributor [Committee Member] | Δολλας Αποστολος | el |
| Contributor [Committee Member] | Papaefstathiou Ioannis | en |
| Contributor [Committee Member] | Παπαευσταθιου Ιωαννης | el |
| Contributor [Co-Supervisor] | Πρατικάκης Πολύβιος | el |
| Contributor [Co-Supervisor] | Pratikakis Polyvios | en |
| Publisher | Πολυτεχνείο Κρήτης | el |
| Publisher | Technical University of Crete | el |
| Academic Unit | Πολυτεχνείο Κρήτης::Σχολή Ηλεκτρονικών Μηχανικών και Μηχανικών Υπολογιστών | el |
| Description | Προπτυχιακή Διατριβή που υποβλήθηκε στη σχολή ΗΜΜΥ του Πολ. Κρήτης για την πλήρωση προϋποθέσεων λήψης του Προπτυχιακού Διπλώματος Ειδίκευσης. | el |
| Content Summary | Mission critical applications rely on both hardware- and software-approaches for fault-tolerance. With the adoption of multiprocessor systems on chip (MPSoCs), processor fault-tolerance with modular redundancy has become a major issue, cost and performance wise. In this thesis first , we augment a task-parallel runtime system with support for transparent checkpoints of task data that may be written during task execution and seamlessly rerun failed tasks. The system can recover from transient errors during task execution within a single core by rerunning the failed task, as well as from permanent errors that disable a worker core by redistributing work among remaining cores. We have evaluated our implementation using six benchmarks and found that checkpointing incurs a performance overhead of 8\% on average, mainly due to the cost of memory copies, and only a negligible space overhead due to the recycling of checkpoint memory. Then, in order to protect the workers runtime system beyond the execution stage, we present ASGUARDIAN, a lightweight hardware mechanism based on a task-oriented model for general programmability. The ASGUARDIAN features both store-and-forward and cut-through capabilities to reliably transfer task descriptions and arguments between main memory and available worker cores. It also isolates the workers from accessing the main memory. A hardware prototype has been implemented on a Xilinx ML605 FPGA board using the widely-used ARM AMBA protocol. Introducing the ASGUARDIAN reliability features results in a 8% average overhead on hardware resources for a configuration with four Microblaze cores. The performance overhead for the store-and-forward and cut-through implementations were 2.3x and 1.2x respectively against an unprotected, shared memory system. When compared against an -unprotected- scratchpad-based memory system, the store-and-forward version showed an overhead of 1.7x, while the cut-through version showed a speedup of 6% on average. | en |
| Type of Item | Διπλωματική Εργασία | el |
| Type of Item | Diploma Work | en |
| License | http://creativecommons.org/licenses/by/4.0/ | en |
| Date of Item | 2014-06-03 | - |
| Date of Publication | 2014 | - |
| Subject | Computing, Fault-tolerant | en |
| Subject | fault tolerant computing | en |
| Subject | computing fault tolerant | en |
| Subject | Computer reliability | en |
| Subject | computers reliability | en |
| Subject | computer reliability | en |
| Subject | CLR (Common Language Runtime) | en |
| Subject | common language runtime computer science | en |
| Subject | clr common language runtime | en |
| Subject | SOC design | en |
| Subject | Systems on chip | en |
| Subject | systems on a chip | en |
| Subject | soc design | en |
| Subject | systems on chip | en |
| Subject | Multicores | en |
| Subject | Task Based Programming Model | en |
| Subject | Field programmable logic arrays | en |
| Subject | FPGAs | en |
| Subject | field programmable gate arrays | en |
| Subject | field programmable logic arrays | en |
| Subject | fpgas | en |
| Bibliographic Citation | Dimitrios Skarlatos, "Reliable runtime architecture for multiprocessor systems on chip", Diploma Work, School of Electronic Engineering, Technical University of Crete, Chania, Greece, 2014 | el |
| Bibliographic Citation | Δημήτριος Σκαρλάτος, "Reliable runtime architecture for multiprocessor systems on chip", Διπλωματική Εργασία, Σχολή Ηλεκτρονικών Μηχανικών και Μηχανικών Υπολογιστών, Πολυτεχνείο Κρήτης, Χανιά, Ελλάς, 2014 | el |
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