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361	Z. Harpantidou, M. Paterakis, "Random multiple access of broadcast channels with Pareto distributed packet interarrival times," Personal Communications, IEEE , vol. 5, no. 2, pp. 48 - 55, 1998, doi: 10.1109/98.667945	2015-11-19
362	A. Dollas and N. Kanopoulos, "Reducing the time to market through rapid prototyping", Computer, vol. 28, no. 2, pp. 14-15, 1995. doi:10.1109/MC.1995.10018	2015-11-18
363	O. Papapetrou, M. Garofalakis, and A. Deligiannakis, "Sketching distributed sliding-window data streams", VLDB J., vol. 24, no. 3, pp. 345-368, Jun. 2015. doi:10.1007/s00778-015-0380-7	2015-11-17
364	D. Sacharidis, A. Deligiannakis, and T. Sellis, "Hierarchically compressed wavelet synopses", VLDB J., vol. 18, no. 1, pp. 203-231, Jan. 2009. doi:10.1007/s00778-008-0096-z	2015-11-17
365	A. Deligiannakis, Y. Kotidis and N. Roussopoulos, "Bandwidth-constrained queries in sensor networks", VLDB J., vol. 17, no. 3, pp. 443-467, May 2008. doi:10.1007/s00778-006-0016-z	2015-11-17
366	M. Katevenis, E. Markatos, G. Kalokerinos and A. Dollas, "Telegraphos: a substrate for high-performance computing on workstation clusters," J. Parallel Distrib. Comput., vol. 43, no. 2 pp. 94-108, Jun. 1997. doi: 10.1006/jpdc.1997.1334	2015-11-17
367	E. Koutroulis, K. Kalaitzakis and A. Dollas, "High frequency pulse width modulation implementation using FPGA and CPLD ICs," J. Syst. Architect., vol. 52, no. 6, pp. 332-344, Jun. 2006. doi: 10.1016/j.sysarc.2005.09.001	2015-11-17
368	A. Deligiannakis, Y. Kotidis, V. Stoumpos and A. Delis, "Collection trees for event-monitoring queries", Inform. Syst., vol. 36, no. 2, pp. 386-405, Apr. 2011. doi:10.1016/j.is.2010.08.003	2015-11-17
369	I. Smonou, S. Khan, C. S. Foote, Y. Elemes, I. Mavridis, A. Pantidou, and M. Orfanopoulos, "Reactions of Phenyltriazolinedione with Alkenes. Stereochemistry and Methanol Adducts to Aziridinium Imide Intermediates", Journal of the American Chemical Society, vol. 117, no. 7081, 1995.	2015-11-16
370	P. Mattheakis, I. Papaefstathiou, "Significantly reducing MPI intercommunication latency and power overhead in both embedded and HPC systems," ACM Transactions on Architecture and Code Optimization, vol. 9, no. 4., Jan., 2013. doi: 10.1145/2400682.2400710	2015-11-16
371	I. Mavroidis, D. Mavroidis, I. Papaefstathiou, "Accelerating Emulation and Providing Full Chip Observability and Controllability," IEEE Design and Test, vol. 26, no. 6, pp. 84-94, Nov./Dec. 2009. doi: 10.1109/MDT.2009.136	2015-11-16
372	D. Simos, I. Papaefstathiou, M. Katevenis, "Towards Fabric-On-a-chip(FoC) : A 400Gbps 32×32 Variable-Packet-Size Buffered Crossbar (CICQ) Single-Chip Switch Core," IEEE Design and Test, to be published.	2015-11-16
373	I. Papaefstathiou, C. Manifavas. (2014). Evaluation of Micropayment Transaction Cost. Journal of Electronic Commerce Research.[Online]. Available: http://web.csulb.edu/journals/jecr/issues/20042/Paper3.pdf	2015-11-16
374	I. Papaefstathiou, A. Nikologiannis, B. Doshi, E. Grosse. (2004,Sept/Oct). Network Processors for Future High-End Systems and Applications. IEEE Micro. [Online]. Available: https://www.computer.org/csdl/mags/mi/2004/05/m5007.pdf	2015-11-16
375	I. Papaefstathiou, S. Perissakis, T. Orphanoudakis, N. Nikolaou, G. Kornaros, D. Pnevmatikatos, G. Konstantoulakis, N. Zervos, "PR03: a hybrid NPU architecture," IEEE Micro, vol. 24, no. 5, pp. 20 - 33, March, 2004. doi: 10.1109/MM.2004.55	2015-11-16
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