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An efficient and low-cost input/output subsystem for network processors

Pnevmatikatos Dionysios, Kyriakos Vlachos, Ioannis Sourdis

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URIhttp://purl.tuc.gr/dl/dias/AEED7410-A42D-41BF-A1EE-78D744786245-
Identifierhttp://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.60.2374&rep=rep1&type=pdf-
Languageen-
Extent 9 pagesen
TitleAn efficient and low-cost input/output subsystem for network processorsen
CreatorPnevmatikatos Dionysiosen
CreatorΠνευματικατος Διονυσιοςel
CreatorKyriakos Vlachosen
CreatorIoannis Sourdisen
Content SummaryWe present the architecture and implementation of an input/output subsystem for a cost-effective network processor. We believe that adding processing power to a networking chip is relatively straightforward. However, transferring data to and from the processor(s) is insufficient for high wire speeds. To address this limitation we use a hardwired input/output subsystem transferring data directly into the processing core’s register file. Using a simple scalar RISC core at 200MHz, we are able to sustain state-full inspection firewall processing at 2.5Gbps TCP traffic.en
Type of ItemPeer-Reviewed Journal Publicationen
Type of ItemΔημοσίευση σε Περιοδικό με Κριτέςel
Licensehttp://creativecommons.org/licenses/by/4.0/en
Date of Item2015-10-19-
Date of Publication2003-
SubjectMonitoring of computer networksen
SubjectNetwork monitoring (Computer networks)en
Subjectcomputer networks monitoringen
Subjectmonitoring of computer networksen
Subjectnetwork monitoring computer networksen
Bibliographic CitationD. Pnevmatikatos, I. Sourdis , K. Vlachos,"An efficient and low-cost input/output subsystem for network processors .(2003).IEEE Design and Test of Computers [online]. pp. 56-64.Available:http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.60.2374&rep=rep1&type=pdfen

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