URI | http://purl.tuc.gr/dl/dias/AEED7410-A42D-41BF-A1EE-78D744786245 | - |
Identifier | http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.60.2374&rep=rep1&type=pdf | - |
Language | en | - |
Extent | 9 pages | en |
Title | An efficient and low-cost input/output subsystem for network processors | en |
Creator | Pnevmatikatos Dionysios | en |
Creator | Πνευματικατος Διονυσιος | el |
Creator | Kyriakos Vlachos | en |
Creator | Ioannis Sourdis | en |
Content Summary | We present the architecture and implementation of an input/output subsystem for a cost-effective network processor. We believe that adding processing power to a networking chip is relatively straightforward. However, transferring data to and from the processor(s) is insufficient for high wire speeds. To address this limitation we use a hardwired input/output subsystem transferring data directly into the processing core’s register file. Using a simple scalar RISC core at 200MHz, we are able to sustain state-full inspection firewall processing at 2.5Gbps TCP traffic. | en |
Type of Item | Peer-Reviewed Journal Publication | en |
Type of Item | Δημοσίευση σε Περιοδικό με Κριτές | el |
License | http://creativecommons.org/licenses/by/4.0/ | en |
Date of Item | 2015-10-19 | - |
Date of Publication | 2003 | - |
Subject | Monitoring of computer networks | en |
Subject | Network monitoring (Computer networks) | en |
Subject | computer networks monitoring | en |
Subject | monitoring of computer networks | en |
Subject | network monitoring computer networks | en |
Bibliographic Citation | D. Pnevmatikatos, I. Sourdis , K. Vlachos,"An efficient and low-cost input/output subsystem for network processors .(2003).IEEE Design and Test of Computers [online]. pp. 56-64.Available:http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.60.2374&rep=rep1&type=pdf | en |