Ιδρυματικό Αποθετήριο
Πολυτεχνείο Κρήτης
Πολυτεχνείο Κρήτης
EN
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EL
| URI: | http://purl.tuc.gr/dl/dias/324FE72B-87A5-447F-931F-99D0EC29EB81 | ||
| Έτος | 2003 | ||
| Τύπος | Πλήρης Δημοσίευση σε Συνέδριο | ||
| Άδεια Χρήσης |
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| Βιβλιογραφική Αναφορά | K. Vlachos, T. Orphanoudakis, N. Nikolaou, S. Perissakis, D. Pnevmatikatos, G. Kornaros, J.A. Sanchez , G. Konstantoulakis, "Processing and scheduling components in an innovative network processor architecture’,"in 2003 Intern. Conf. on VLSI Design, pp.195 - 201.doi:10.1109/ICVD.2003.1183136 https://doi.org/10.1109/ICVD.2003.1183136 | ||
| Εμφανίζεται στις Συλλογές |
In this paper, we describe the architecture of an innovative network processor aiming at the acceleration of packet processing in high speed network interfaces and at the tight coupling of low and high level protocols. The proposed design uses programmable hard-wired components with line rate throughput and is capable of executing protocols and handling efficiently high and low level streaming operations. We discuss the details of the main innovation of the proposed design, which incorporates a three stage RISC-based pipelined module and a composite scheduling unit for internal resource management and outgoing traffic shaping. When both components are integrated on the same platform then maximum and fair utilization of the available resources is achieved. Quantitative performance results are given, both by means of microcode profiling and simulation for indicative applications of the protocol processor.
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