Institutional Repository
Technical University of Crete
Technical University of Crete
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| URI: | http://purl.tuc.gr/dl/dias/79686747-3F9D-45E5-85D2-E4B32BC390E7 | ||
| Year | 2007 | ||
| Type of Item | Conference Full Paper | ||
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| Bibliographic Citation | V. Papaefstathiou, D. N. Pnevmatikatos, M. Marazakis, G. Kalokairinos, A. Ioannou, M. Papamichael, S. Kavadias, G. Mihelogiannakis, M. Katevenis," Prototyping efficient interprocessor communication mechanisms"in 2007 Intern. Confe. on Embedded Comp. Systems: Architectures, Modelling and Simulation,pp.26 - 33.doi:10.1109/ICSAMOS.2007.4285730 https://doi.org/10.1109/ICSAMOS.2007.4285730 | ||
| Appears in Collections |
Parallel computing systems are becoming widespread and grow in sophistication. Besides simulation, rapid system prototyping becomes important in designing and evaluating their architecture. We present an efficient FPGA-based platform that we developed and use for research and experimentation on high speed interprocessor communication, network interfaces and interconnects. Our platform supports advanced communication capabilities such as remote DMA, remote queues, zero-copy data delivery and flexible notification mechanisms, as well as link bundling for increased performance. We report on the platform architecture, its design cost, complexity and performance (latency and throughput). We also report our experiences from implementing benchmarking kernels and a user-level benchmark application, and show how software can take advantage of the provided features, but also expose the weaknesses of the system.
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