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Least-squares iterative solution on a fixed-size VLSI architecture

T. S. Papatheodorou, Papadopoulou Eleni

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URI: http://purl.tuc.gr/dl/dias/15FC95C4-8755-4EFC-AEE9-07495E93EEF8
Year 2005
Type of Item Peer-Reviewed Journal Publication
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Bibliographic Citation Least Squares Iterative Solution on a Fixed Size VLSI Architecture , E.P. Papadopoulou, T.S. Papatheodorou, Springer Verlag Lecture Notes in Computer Science, Vol.297, pp. 914-925. May 2005
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Summary

The VLSI implementation of the Accelerated Overrelaxation (AOR) method, when used for the accurate computation of the least-squares solutions of overdetermined systems, is the problem addressed here. As the size of this computational task is usually very large, we use space-time domain expansion techniques to partition the computation and map it onto a fixed size VLSI architecture.

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