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Technical University of Crete
Technical University of Crete
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| URI | http://purl.tuc.gr/dl/dias/4AF484DD-3EFC-4EC4-95B7-3C61F7A3BB93 | - |
| Identifier | http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=5463267&url=http%3A%2F%2Fieeexplore.ieee.org%2Fiel5%2F19%2F5463259%2F05463267.pdf%3Farnumber%3D5463267 | - |
| Identifier | https://doi.org/10.1109/TIM.2009.2026607 | - |
| Language | en | - |
| Extent | 10 pages | en |
| Title | An effective framework to evaluate dynamic partial reconfiguration in FPGA systems | en |
| Creator | Papadimitriou Kyprianos | en |
| Creator | Παπαδημητριου Κυπριανος | el |
| Creator | Anyfantis Antonis | en |
| Creator | Dollas Apostolos | en |
| Creator | Δολλας Αποστολος | el |
| Publisher | Institute of Electrical and Electronics Engineers | en |
| Content Summary | The most popular representative devices of reconfigurable computing are field-programmable gate arrays (FPGAs). A promising feature of an FPGA is the ability to reuse the same hardware for different tasks at different phases of an application execution. Moreover, the tasks can be swapped on the fly while part of the hardware continues to operate. This is known as dynamic reconfiguration, and evaluation of its performance presents interesting research challenges. This paper introduces a general framework for measuring the reconfiguration time from the system perspective. In addition, a methodology for setting up different system parameters and automatically gathering and processing the experimental results has been developed. It is proven that these parameters affect the applications designed in a dynamically reconfigurable system, and rapid evaluation enables quick examination of their impact on performance. Results demonstrate the usefulness of the framework. | en |
| Type of Item | Peer-Reviewed Journal Publication | en |
| Type of Item | Δημοσίευση σε Περιοδικό με Κριτές | el |
| License | http://creativecommons.org/licenses/by/4.0/ | en |
| Date of Item | 2015-11-02 | - |
| Date of Publication | 2010 | - |
| Subject | Field programmable gate arrays | en |
| Subject | Programmable logic arrays | en |
| Subject | Hardware | en |
| Subject | Random access memory | en |
| Subject | Application software | en |
| Subject | Protocols | en |
| Subject | Time measurement | en |
| Subject | Reconfigurable architectures | en |
| Subject | System analysis and design | en |
| Subject | Circuits | en |
| Bibliographic Citation | K. Papadimitriou, A. Anyfantis and A. Dollas, "An effective framework to evaluate dynamic partial reconfiguration in FPGA systems," IEEE Trans. Instrum. Meas., vol. 59, no. 6, pp. 1642-1651, Jun. 2010. doi:10.1109/TIM.2009.2026607 | en |
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