Institutional Repository
Technical University of Crete
Technical University of Crete
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| URI: | http://purl.tuc.gr/dl/dias/4DE6CF6C-8F88-4CBA-8267-0DFA1D2291B9 | ||
| Year | 1994 | ||
| Type of Item | Peer-Reviewed Journal Publication | ||
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| Bibliographic Citation | K. Boland and A. Dollas, "Predicting and precluding problems with memory latency", IEEE Micro, vol. 14, no. 4, pp. 59-67, Aug. 1994. doi:10.1109/40.296166 https://doi.org/10.1109/40.296166 | ||
| Appears in Collections |
By examining the rate at which successive generations of processor and DRAM cycle times have been diverging over time, we can track the latency problem of computer memory systems. Our research survey starts with the fundamentals of single-level caches and moves to the need for multilevel cache hierarchies. We look at some of the current techniques for boosting cache performance, especially compiler-based methods for code restructuring and instruction and data prefetching. These two areas will likely yield improvements for a much larger domain of applications in the future.
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