Institutional Repository
Technical University of Crete
EN  |  EL

Search

Browse

My Space

Predicting and precluding problems with memory latency

Boland K. , Dollas Apostolos

Simple record


URIhttp://purl.tuc.gr/dl/dias/4DE6CF6C-8F88-4CBA-8267-0DFA1D2291B9-
Identifierhttp://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=296166&url=http%3A%2F%2Fieeexplore.ieee.org%2Fiel1%2F40%2F7325%2F00296166.pdf%3Farnumber%3D296166-
Identifierhttps://doi.org/10.1109/40.296166-
Languageen-
Extent9 pagesen
TitlePredicting and precluding problems with memory latencyen
CreatorBoland K. en
CreatorDollas Apostolosen
CreatorΔολλας Αποστολοςel
PublisherInstitute of Electrical and Electronics Engineersen
Content SummaryBy examining the rate at which successive generations of processor and DRAM cycle times have been diverging over time, we can track the latency problem of computer memory systems. Our research survey starts with the fundamentals of single-level caches and moves to the need for multilevel cache hierarchies. We look at some of the current techniques for boosting cache performance, especially compiler-based methods for code restructuring and instruction and data prefetching. These two areas will likely yield improvements for a much larger domain of applications in the future.en
Type of ItemPeer-Reviewed Journal Publicationen
Type of ItemΔημοσίευση σε Περιοδικό με Κριτέςel
Licensehttp://creativecommons.org/licenses/by/4.0/en
Date of Item2015-11-02-
Date of Publication1994-
SubjectDelayen
SubjectRandom access memoryen
SubjectThroughputen
SubjectClocksen
SubjectMicroprocessorsen
SubjectContent addressable storageen
SubjectBoostingen
SubjectPrefetchingen
SubjectApplication softwareen
SubjectMicrocomputersen
Bibliographic CitationK. Boland and A. Dollas, "Predicting and precluding problems with memory latency", IEEE Micro, vol. 14, no. 4, pp. 59-67, Aug. 1994. doi:10.1109/40.296166en

Services

Statistics