URI | http://purl.tuc.gr/dl/dias/4DE6CF6C-8F88-4CBA-8267-0DFA1D2291B9 | - |
Identifier | http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=296166&url=http%3A%2F%2Fieeexplore.ieee.org%2Fiel1%2F40%2F7325%2F00296166.pdf%3Farnumber%3D296166 | - |
Identifier | https://doi.org/10.1109/40.296166 | - |
Language | en | - |
Extent | 9 pages | en |
Title | Predicting and precluding problems with memory latency | en |
Creator | Boland K. | en |
Creator | Dollas Apostolos | en |
Creator | Δολλας Αποστολος | el |
Publisher | Institute of Electrical and Electronics Engineers | en |
Content Summary | By examining the rate at which successive generations of processor and DRAM cycle times have been diverging over time, we can track the latency problem of computer memory systems. Our research survey starts with the fundamentals of single-level caches and moves to the need for multilevel cache hierarchies. We look at some of the current techniques for boosting cache performance, especially compiler-based methods for code restructuring and instruction and data prefetching. These two areas will likely yield improvements for a much larger domain of applications in the future. | en |
Type of Item | Peer-Reviewed Journal Publication | en |
Type of Item | Δημοσίευση σε Περιοδικό με Κριτές | el |
License | http://creativecommons.org/licenses/by/4.0/ | en |
Date of Item | 2015-11-02 | - |
Date of Publication | 1994 | - |
Subject | Delay | en |
Subject | Random access memory | en |
Subject | Throughput | en |
Subject | Clocks | en |
Subject | Microprocessors | en |
Subject | Content addressable storage | en |
Subject | Boosting | en |
Subject | Prefetching | en |
Subject | Application software | en |
Subject | Microcomputers | en |
Bibliographic Citation | K. Boland and A. Dollas, "Predicting and precluding problems with memory latency", IEEE Micro, vol. 14, no. 4, pp. 59-67, Aug. 1994. doi:10.1109/40.296166 | en |