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The evolution of instruction sequencing

Krick R. F., Dollas Apostolos

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URIhttp://purl.tuc.gr/dl/dias/922B0612-5A30-4685-AD37-4EBF6CF87BC5-
Identifierhttp://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=76259&url=http%3A%2F%2Fieeexplore.ieee.org%2Fiel1%2F2%2F2541%2F00076259-
Identifierhttps://doi.org/10.1109/2.76259-
Languageen-
Extent11 pagesen
TitleThe evolution of instruction sequencingen
CreatorKrick R. F.en
CreatorDollas Apostolosen
CreatorΔολλας Αποστολοςel
PublisherInstitute of Electrical and Electronics Engineersen
Content SummaryThe three distinct phases that constitute the sequencing of an instruction are determining the memory address that contains the instruction, fetching the instruction from memory, and executing the instruction. The evolution of instruction sequencing is traced, with attention focused on the influence of the available technology on the minimum time required for each of these phases and the resulting design decisions. Rather than absolute system performance. the interrelationship of these critical parameters is examined. Memory bandwidth, instruction buffers, caches, and the impact of reduced-instruction-set computers (RISCs) are discussed. Recent innovations are described, and the options and constraints that designers face with respect to future developments are evaluated.en
Type of ItemPeer-Reviewed Journal Publicationen
Type of ItemΔημοσίευση σε Περιοδικό με Κριτέςel
Licensehttp://creativecommons.org/licenses/by/4.0/en
Date of Item2015-11-03-
Date of Publication1991-
SubjectBandwidthen
SubjectRandom access memoryen
SubjectInterleaved codesen
SubjectTelluriumen
SubjectMagnetic coresen
SubjectSemiconductor memoryen
SubjectBipolar transistorsen
SubjectSystem performanceen
SubjectTerminologyen
SubjectContext modelingen
Bibliographic CitationR. Krick and A. Dollas, "The evolution of instruction sequencing", IEEE Comput., vol. 24, no. 4, pp. 5-15, Apr. 1991. doi:10.1109/2.76259en

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