Institutional Repository
Technical University of Crete
Technical University of Crete
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| URI: | http://purl.tuc.gr/dl/dias/1264D237-A398-45C8-ABDA-4CDEB1E28E5D | ||
| Year | 2015 | ||
| Type of Item | Conference Full Paper | ||
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| Bibliographic Citation | G. Charitopoulos, D. Pnevmatikatos, M. SantambrogioK. Papadimitriou and D. Pau, "A Run-Time System for Partially Reconfigurable FPGAs: The case of STMicroelectronics SPEAr board", in ParaFPGA: Parallel Computing with FPGAs, in conjunction with the International Conference on Parallel Computing (ParCo), Sep. 2015. | ||
| Appears in Collections |
During recent years much research focused on making Partial Reconfiguration (PR)more widespread. The FASTER project aimed at realizing an integrated toolchainthat assists the designer in the steps of the design flow that are necessary to port agiven application onto an FPGA device. The novelty of the framework lies in theuse of partial dynamic reconfiguration seen as a first class citizen throughout theentire design flow in order to exploit FPGA device potential.The STMicroelectronics SPEAr development platform combines an ARM processoralongside with a Virtex-5 FPGA daughter-board. While partial reconfigurationin the attached board was considered as feasible from the beginning, there wasno full implementation of a hardware architecture using PR. This work describesour efforts to exploit PR on the SPEAr prototyping embedded platform. The paperdiscusses the implemented architecture, as well as the integration of Run-TimeSystem Manager for scheduling (run-time reconfiogurable) hardware and softwaretasks. We also propose improvements that can be exploited in order to make the PRutility more easy-to-use on future projects on the SPEAr platform.
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