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Enabling dynamically reconfigurable technologies in mid range computers through PCI express

Vatsolakis Charalabos, Papadimitriou Kyprianos, Pnevmatikatos Dionysios

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Summary

Efficient I/O access is crucial in reconfigurable hardwareplatforms for implementing high-performance systems. Such platformscan outperform CPUs and GPGPUs in executing applications characterizedby inherent parallelism. However, the system-level performancedepends heavily on sustaining high transfer rates for feeding data intothe reconfigurable hardware and getting the results back to the end-user.In the present work we propose and implement a hybrid system comprisinga host computer and an FPGA platform. The latter acts as coprocessorinto which hardware accelerators are loaded and executed in atransparent way, i.e. user is not involved in FPGA programming neithercontrolling its execution. Depending on the user request, the FPGA canbe reconfigured either partially or entirely. Initially, we discuss the currentstate-of-the-art on I/O interfaces attached to FPGAs focusing primarilyon the PCI Express (PCIe). Then, we present our system on whichwe implemented a design for measuring end-to-end throughput. We havedeveloped a simple yet functional interface for serving the communicationbetween software and hardware over PCIe v1.0 bus. At system-level,we achieved a throughput of 544 MBytes/s and 618 MBytes/s for DMAwrites and reads respectively, over a PCIe four-lane (x4) connection. Thisincludes all overhead such as communication delays and systems calls forrequesting services from the operating system. Our work can be used asthe basis for programming and executing hardware accelerators underthe control of a run-time system.

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