Institutional Repository
Technical University of Crete
Technical University of Crete
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| URI: | http://purl.tuc.gr/dl/dias/2E740457-4C8A-4060-9B99-747E219CA9D6 | ||
| Year | 2013 | ||
| Type of Item | Conference Full Paper | ||
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| Bibliographic Citation | M.D. Santambrogio, C. Pilato, D. Pnevmatikatos, K. Papadimitriou, D. Stroobandt and D. Sciuto, "The FASTER Vision for Designing Dynamically Reconfigurable Systems, in IEEE International Conference on IC Design and Technology (ICICDT), May 2013. | ||
| Appears in Collections |
Extending product functionality and lifetime requiresconstant addition of new features to satisfy the growingcustomer needs and the evolving market and technologytrends. software component adaptivity is straightforward but notenough: recent products include hardware accelerators for reasonsof performance and power efficiency that also need to adaptto new requirements. Reconfigurable logic allows the definitionof new functions to be implemented in dynamically instantiatedhardware units, combining adaptivity with hardware speed andefficiency. For the Intrusion Detection System example, new rulescan be hardcoded into the reconfigurable logic, achieving highperformance, while providing the necessary adaptivity to newthreats.The FASTER (Facilitating Analysis and Synthesis Technologiesfor Effective Reconfiguration) project aims at introducing acomplete methodology to allow designers to easily implement asystem specification on a platform combining a general purposeprocessor with multiple accelerators running on an FPGA,taking as input a high-level description and fully exploiting,both at design- and run-time, the capabilities of partial dynamicreconfiguration. The FASTER project will facilitate the use ofreconfigurable hardware by providing a complete methodologythat enables designers to easily implement and verify applicationson platforms with general-purpose processors and accelerationmodules implemented in the latest reconfigurable technology.
Copyright © DIAS 2013
