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Novel design methods and a tool flow for unleashing dynamic reconfiguration

Papadimitriou Kyprianos, Pilato Christian , Pnevmatikatos Dionysios, Santambrogio Marco D., Ciobanu Catalin Bogdan, Todman Tod, Becker Tobias, Davidson Tom, Niu Xinyu, Gaydadjiev Georgi, Luk Wayne, Stroobandt Dirk

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Περίληψη

During the last few years, there is an increasinginterest in mixing software and hardware to serve efficientlydifferent applications. This is due to the heterogeneity characterizingthe tasks of an application which require the presence ofresources from both worlds, software and hardware. Controllingeffectively these resources through an integrated tool flow is achallenging problem and towards this direction only a few effortsexist. In fact, a framework that seamlessly exploits both resourcesof a platform for executing efficiently an application has not yetcome into existence. Moreover, reconfigurable computing oftenincorporated in such platforms due to its high flexibility andcustomization, has not yet taken off due to the lack of exploitingits full capabilities. Thus, the capability of reconfigurabledevices such as Field Programmable Gate Arrays (FPGAs) to bedynamically reconfigured, i.e. reprogramming part of the chipwhile other parts of the same chip remain functional, has notyet taken off even in small-scale basis. The inherent difficulty inusing the tools to control this technology has kept it back frombeing adopted by academia and industry alike.The FASTER (Facilitating Analysis and Synthesis Technologiesfor Effective Reconfiguration) project aims at introducing adesign methodology and a tool flow that will enable designersto implement effectively and easily a system specification on aplatform combining software and reconfigurable resources. TheFASTER framework accepts as input a high-level descriptionof the application and the architectural details of the targetplatform, and through certain steps it can enable the full useof the capabilities of the platform, while at the same time itshould be flexible enough so as to balance efficiently performance,power and area. One of the main novelties is the incorporation ofpartial reconfiguration as an explicit design concept at an earlystage of the design flow. We target different applications from theembedded, desktop and high-performance computing domains.In all cases we will demonstrate the effectiveness of the proposedframework in exploiting the inherent parallelism of applicationsand enabling the runtime adaptation of the platforms to thechanging needs of the applications.

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