Ιδρυματικό Αποθετήριο
Πολυτεχνείο Κρήτης
Πολυτεχνείο Κρήτης
EN
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| URI: | http://purl.tuc.gr/dl/dias/5AD366BB-71B3-4993-ACB6-905ADBBCC99B | ||
| Έτος | 2012 | ||
| Τύπος | Πλήρης Δημοσίευση σε Συνέδριο | ||
| Άδεια Χρήσης |
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| Βιβλιογραφική Αναφορά | M.D. Santambrogio, D. Pnevmatikatos, K. Papadimitriou, C. Pilato, G. Gaydadjiev, D. Stroobandt, T. Davidson, T. Becker, T. Todman, W. Luk, A. Bonetto, A. Cazzaniga, G.C. Durelli and D. Sciuto, "Smart Technologies for Effective Reconfiguration: The FASTER Approach", in IEEE International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), July 2012. | ||
| Εμφανίζεται στις Συλλογές |
Current and future computing systems increasinglyrequire that their functionality stays flexible after the system isoperational, in order to cope with changing user requirementsand improvements in system features, i.e. changing protocols anddata-coding standards, evolving demands for support of differentuser applications, and newly emerging applications in communication,computing and consumer electronics. Therefore, extendingthe functionality and the lifetime of products requires theaddition of new functionality to track and satisfy the customersneeds and market and technology trends. Many contemporaryproducts along with the software part incorporate hardwareaccelerators for reasons of performance and power efficiency.While adaptivity of software is straightforward, adaptation ofthe hardware to changing requirements constitutes a challengingproblem requiring delicate solutions.The FASTER (Facilitating Analysis and Synthesis Technologiesfor Effective Reconfiguration) project aims at introducing acomplete methodology to allow designers to easily implementa system specification on a platform which includes a generalpurpose processor combined with multiple accelerators runningon an FPGA, taking as input a high-level description and fullyexploiting, both at design time and at run time, the capabilitiesof partial dynamic reconfiguration. The goal is that for selectedapplication domains, the FASTER toolchain will be able toreduce the design and verification time of complex reconfigurablesystems providing additional novel verification features that arenot available in existing tool flows.
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