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Smart technologies for effective reconfiguration: the FASTER approach

Santambrogio Marco D., Pnevmatikatos Dionysios, Papadimitriou Kyprianos, Pilato Christian, Gaydadjiev Georgi, Stroobandt Dirk, Davidson Tom, Todman Tod, Becker Tobias, Luk Wayne, Bonetto Alessandra, Cazzaniga Andrea, Durelli Gianluca, Sciuto Donatella

Απλή Εγγραφή

URIhttp://purl.tuc.gr/dl/dias/5AD366BB-71B3-4993-ACB6-905ADBBCC99B-
Αναγνωριστικόhttp://users.isc.tuc.gr/~kpapadimitriou/publications/2012recosoc-faster.pdf-
Γλώσσαen-
ΤίτλοςSmart technologies for effective reconfiguration: the FASTER approachen
ΔημιουργόςSantambrogio Marco D.en
ΔημιουργόςPnevmatikatos Dionysiosen
ΔημιουργόςΠνευματικατος Διονυσιοςel
ΔημιουργόςPapadimitriou Kyprianosen
ΔημιουργόςΠαπαδημητριου Κυπριανοςel
ΔημιουργόςPilato Christianen
ΔημιουργόςGaydadjiev Georgien
ΔημιουργόςStroobandt Dirken
ΔημιουργόςDavidson Tomen
ΔημιουργόςTodman Toden
ΔημιουργόςBecker Tobiasen
ΔημιουργόςLuk Wayneen
ΔημιουργόςBonetto Alessandraen
ΔημιουργόςCazzaniga Andreaen
ΔημιουργόςDurelli Gianlucaen
ΔημιουργόςSciuto Donatellaen
ΕκδότηςInstitute of Electrical and Electronics Engineersen
ΠερίληψηCurrent and future computing systems increasingly require that their functionality stays flexible after the system is operational, in order to cope with changing user requirements and improvements in system features, i.e. changing protocols and data-coding standards, evolving demands for support of different user applications, and newly emerging applications in communication, computing and consumer electronics. Therefore, extending the functionality and the lifetime of products requires the addition of new functionality to track and satisfy the customers needs and market and technology trends. Many contemporary products along with the software part incorporate hardware accelerators for reasons of performance and power efficiency. While adaptivity of software is straightforward, adaptation of the hardware to changing requirements constitutes a challenging problem requiring delicate solutions. The FASTER (Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration) project aims at introducing a complete methodology to allow designers to easily implement a system specification on a platform which includes a general purpose processor combined with multiple accelerators running on an FPGA, taking as input a high-level description and fully exploiting, both at design time and at run time, the capabilities of partial dynamic reconfiguration. The goal is that for selected application domains, the FASTER toolchain will be able to reduce the design and verification time of complex reconfigurable systems providing additional novel verification features that are not available in existing tool flows.en
ΤύποςΠλήρης Δημοσίευση σε Συνέδριοel
ΤύποςConference Full Paperen
Άδεια Χρήσηςhttp://creativecommons.org/licenses/by/4.0/en
Ημερομηνία2015-11-12-
Ημερομηνία Δημοσίευσης2012-
Θεματική ΚατηγορίαInformaticsen
Θεματική Κατηγορίαcomputer scienceen
Θεματική Κατηγορίαinformaticsen
Βιβλιογραφική ΑναφοράM.D. Santambrogio, D. Pnevmatikatos, K. Papadimitriou, C. Pilato, G. Gaydadjiev, D. Stroobandt, T. Davidson, T. Becker, T. Todman, W. Luk, A. Bonetto, A. Cazzaniga, G.C. Durelli and D. Sciuto, "Smart Technologies for Effective Reconfiguration: The FASTER Approach", in IEEE International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), July 2012.en

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