Institutional Repository
Technical University of Crete
Technical University of Crete
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| URI | http://purl.tuc.gr/dl/dias/5AD366BB-71B3-4993-ACB6-905ADBBCC99B | - |
| Identifier | http://users.isc.tuc.gr/~kpapadimitriou/publications/2012recosoc-faster.pdf | - |
| Language | en | - |
| Title | Smart technologies for effective reconfiguration: the FASTER approach | en |
| Creator | Santambrogio Marco D. | en |
| Creator | Pnevmatikatos Dionysios | en |
| Creator | Πνευματικατος Διονυσιος | el |
| Creator | Papadimitriou Kyprianos | en |
| Creator | Παπαδημητριου Κυπριανος | el |
| Creator | Pilato Christian | en |
| Creator | Gaydadjiev Georgi | en |
| Creator | Stroobandt Dirk | en |
| Creator | Davidson Tom | en |
| Creator | Todman Tod | en |
| Creator | Becker Tobias | en |
| Creator | Luk Wayne | en |
| Creator | Bonetto Alessandra | en |
| Creator | Cazzaniga Andrea | en |
| Creator | Durelli Gianluca | en |
| Creator | Sciuto Donatella | en |
| Publisher | Institute of Electrical and Electronics Engineers | en |
| Content Summary | Current and future computing systems increasingly require that their functionality stays flexible after the system is operational, in order to cope with changing user requirements and improvements in system features, i.e. changing protocols and data-coding standards, evolving demands for support of different user applications, and newly emerging applications in communication, computing and consumer electronics. Therefore, extending the functionality and the lifetime of products requires the addition of new functionality to track and satisfy the customers needs and market and technology trends. Many contemporary products along with the software part incorporate hardware accelerators for reasons of performance and power efficiency. While adaptivity of software is straightforward, adaptation of the hardware to changing requirements constitutes a challenging problem requiring delicate solutions. The FASTER (Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration) project aims at introducing a complete methodology to allow designers to easily implement a system specification on a platform which includes a general purpose processor combined with multiple accelerators running on an FPGA, taking as input a high-level description and fully exploiting, both at design time and at run time, the capabilities of partial dynamic reconfiguration. The goal is that for selected application domains, the FASTER toolchain will be able to reduce the design and verification time of complex reconfigurable systems providing additional novel verification features that are not available in existing tool flows. | en |
| Type of Item | Πλήρης Δημοσίευση σε Συνέδριο | el |
| Type of Item | Conference Full Paper | en |
| License | http://creativecommons.org/licenses/by/4.0/ | en |
| Date of Item | 2015-11-12 | - |
| Date of Publication | 2012 | - |
| Subject | Informatics | en |
| Subject | computer science | en |
| Subject | informatics | en |
| Bibliographic Citation | M.D. Santambrogio, D. Pnevmatikatos, K. Papadimitriou, C. Pilato, G. Gaydadjiev, D. Stroobandt, T. Davidson, T. Becker, T. Todman, W. Luk, A. Bonetto, A. Cazzaniga, G.C. Durelli and D. Sciuto, "Smart Technologies for Effective Reconfiguration: The FASTER Approach", in IEEE International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), July 2012. | en |
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