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Methodology and experimental setup for the determination of system-level dynamic reconfiguration overhead

Papadimitriou Kyprianos, Anyfantis Antonis, Dollas Apostolos

Πλήρης Εγγραφή

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Περίληψη

Dynamic reconfiguration is gaining popularity [2], [4]but it may cause degradation of overall execution time dueto the time to download the bitstream before an applicationstarts execution of the new configuration. Thus evaluationof its performance becomes an interesting area [3]. In thiswork we include an analysis of the reconfiguration time bydefining the delays that add up to it. An experimental setupis deployed that can be used for performance evaluation ofapplications implemented with dynamic reconfiguration, aswell as of mechanisms developed to reduce reconfigurationoverhead.The configuration memory of Xilinx Virtex-II is arrangedin vertical frames. In a self-reconfigurable system[1] where the PowerPC reconfigures the FPGA through theInternal Configuration Access Port (ICAP), once data areavailable in the configuration cache HWICAP BRAM thenominal time to reconfigure a single frame is 12.5 µs for 66MHz. However, this is not the only aspect in the reconfigurationprocess. Several physical components of the systemadd significant delays causing reconfiguration time to increasemore than three orders of magnitude as compared tothe above time.

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