Institutional Repository
Technical University of Crete
Technical University of Crete
EN
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EL
| URI | http://purl.tuc.gr/dl/dias/8C5ACDDD-0A6E-4CCB-8599-731E4A04FAEE | - |
| Identifier | http://link.springer.com/article/10.1023/B%3AIJPP.0000004512.53221.ff | - |
| Identifier | https://doi.org/10.1023/B:IJPP.0000004512.53221.ff | - |
| Language | en | - |
| Extent | 18 pages | en |
| Title | A reconfigurable logic-based processor for the SCAN image and video encryption algorithm | en |
| Creator | Dollas Apostolos | en |
| Creator | Δολλας Αποστολος | el |
| Creator | Bourbakis, Nikolaos G | en |
| Creator | Kachris, Christoforos | en |
| Publisher | Kluwer | en |
| Content Summary | This paper presents a detailed architecture and a reconfigurable logic based hardware design of the SCAN algorithm. This architecture can be used to encrypt high resolution images in real-time. Although the SCAN algorithm is a block cipher algorithm with arbitrarily large blocks, the present design is for 64×64 pixel blocks in order to provide real-time image encryption throughput. The architecture was initially targeted at the Xilinx XCV-1000 FPGA, for which design and performance results are presented in the paper. | en |
| Type of Item | Peer-Reviewed Journal Publication | en |
| Type of Item | Δημοσίευση σε Περιοδικό με Κριτές | el |
| License | http://creativecommons.org/licenses/by/4.0/ | en |
| Date of Item | 2015-11-14 | - |
| Date of Publication | 2003 | - |
| Subject | Reconfigurable logic | en |
| Subject | Image encryption | en |
| Subject | Block cipher | en |
| Subject | Cryptography | en |
| Bibliographic Citation | C. Kachris, N. Bourbakis and A. Dollas, "A reconfigurable logic-based processor for the SCAN image and video encryption algorithm," Int. J. Parall. Programm., vol. 31, no. 6, pp. 489-506, Dec. 2003. doi:10.1023/B:IJPP.0000004512.53221.ff | en |
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