Ιδρυματικό Αποθετήριο
Πολυτεχνείο Κρήτης
Πολυτεχνείο Κρήτης
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| URI: | http://purl.tuc.gr/dl/dias/C4CB74AC-6BFD-4174-A0F8-C105BA5F913F | ||
| Έτος | 2007 | ||
| Τύπος | Πλήρης Δημοσίευση σε Συνέδριο | ||
| Άδεια Χρήσης |
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| Βιβλιογραφική Αναφορά | D. Meidanis, I. Papaefstathiou I., "An efficient FPGA-based implementation of Pollard's (rho-1) factorization algorithm," in International Conference: Field-Programmable Technology, 2007. doi: 10.1109/FPT.2007.4439287 https://doi.org/ 10.1109/FPT.2007.4439287 | ||
| Εμφανίζεται στις Συλλογές |
Due to the widespread use of public key cryptosystems whose security depends on the presumed difficulty of the factorization problem, the algorithms for finding the prime factors of large composite numbers are becoming extremely important. In recent years the limits of the best integer factorization algorithms have been extended greatly, due in part to Moore's law and in part to algorithmic improvements. Furthermore, new silicon devices, such as FPGAs, give us the advantage of custom hardware architectures for minimizing execution time for such difficult computations. This paper demonstrates a very efficient FPGA-based design executing Pollard's (rho - 1) factorization algorithm. The proposed device offers a speedup from 20 to 231 when compared to the software implementation of the same algorithm in a state-of-the-art CPU.
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