Ιδρυματικό Αποθετήριο
Πολυτεχνείο Κρήτης
Πολυτεχνείο Κρήτης
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| URI | http://purl.tuc.gr/dl/dias/DDDD8D84-CF57-41F4-B5CA-7F2C8E762EB3 | - |
| Αναγνωριστικό | https://doi.org/10.1109/ICC.2008.399 | - |
| Γλώσσα | en | - |
| Τίτλος | A Multi gigabit FPGA-based 5-tuple classification system | en |
| Δημιουργός | Papaefstathiou Ioannis | en |
| Δημιουργός | Παπαευσταθιου Ιωαννης | el |
| Δημιουργός | Nikitakis Antonios | en |
| Δημιουργός | Νικητακης Αντωνιος | el |
| Εκδότης | Institute of Electrical and Electronics Engineers | en |
| Περίληψη | Packet classification is one of the most important enabling technologies for next generation network services. Even though many multi-dimensional classification algorithms have been proposed, most of them are precluded from commercial equipments due to their high memory requirements. In this paper, we present an efficient packet classification scheme, called dual stage bloom filter classification engine (2sBFCE). 2sBFC comprises of an innovative 5- field search scheme that decomposes multi-field classification rules into internal single-field rules which are combined using multi-level Bloom filters. The design of 2sBFCE is optimized for the common case based on analysis of real world classification databases. The hardware implementation of this scheme handles 4 K rules while supporting network streams at a rate of 2 Gbps even in the worst case, and more than 6 Gbps in the average case when implemented in an off-the-shelf FPGA. | en |
| Τύπος | Πλήρης Δημοσίευση σε Συνέδριο | el |
| Τύπος | Conference Full Paper | en |
| Άδεια Χρήσης | http://creativecommons.org/licenses/by/4.0/ | en |
| Ημερομηνία | 2015-11-15 | - |
| Ημερομηνία Δημοσίευσης | 2008 | - |
| Βιβλιογραφική Αναφορά | I. Papaefstathiou, A. Nikitakis, "A Multi Gigabit FPGA-Based 5-tuple Classification System," in IEEE International Conference on Communications, 2008, pp. 2081 - 2085. doi: 10.1109/ICC.2008.399 | en |
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