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Technical University of Crete
Technical University of Crete
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| URI: | http://purl.tuc.gr/dl/dias/04F12384-A20C-4DED-A7D6-E7CDBD07D0DE | ||
| Year | 2004 | ||
| Type of Item | Conference Full Paper | ||
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| Bibliographic Citation | I. Papaefstathiou, G. Kornaros, N. Zervos, "Software processing performance in network processors," in IEEE Design Automation and Test in Europe, 2004, pp. 186 - 191. doi: 10.1109/DATE.2004.1269228 https://doi.org/10.1109/DATE.2004.1269228 | ||
| Appears in Collections |
To meet the demand for higher performance, flexibility, and economy in today's state-of-the-art networks, an alternative to the ASICs that traditionally were used to implement packet-processing functions in hardware, called network processors (NPs), has emerged. In this paper, we briefly outline the architecture of such an innovative network processor aiming at the acceleration of protocol processing in high-speed network interfaces, and we use this architecture as a case study for our measurements. We focus on the performance of the general purpose processors used for executing high level protocol processing, since this part proves to be the bottleneck of the design. The performance is analyzed by executing a set of widely used, real applications and by applying network traffic according to certain stochastic criteria. The performance of the RISC used is compared with that of other well-known CPU architectures so as to verify that our results are applicable to the general network processors era. As our results demonstrate, the bottleneck of the majority of the network processors is the general-purpose processing units used, since today's network protocols need a great amount of high-level processing. On the other hand the specific purpose processors or co-processors, optimized for certain part of the network packet processing, involved in such systems, can provide the power needed, even at today's ultra high network speeds.
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