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An IRAM-based architecture for a single-chip ATM switch

Papaefstathiou Ioannis, Brown A., Simer J., Sobel D., Sutaria J., Wang Y., Blackwell T., Smith M., Yang W.

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URIhttp://purl.tuc.gr/dl/dias/8A69A5A6-ECFD-4D8E-9BF4-B02A2C97C0C0-
Identifierhttps://doi.org/10.1109/ICECS.1999.812232-
Languageen-
TitleAn IRAM-based architecture for a single-chip ATM switchen
CreatorPapaefstathiou Ioannisen
CreatorΠαπαευσταθιου Ιωαννηςel
CreatorBrown A.en
CreatorSimer J.en
CreatorSobel D.en
CreatorSutaria J.en
CreatorWang Y.en
CreatorBlackwell T.en
Creator Smith M.en
CreatorYang W.en
PublisherInstitute of Electrical and Electronics Engineersen
Content SummaryWe have developed an architecture for an IRAM-based ATM switch that is implemented with merged DRAM and logic for a cost of about $100. The switch is based on a shared buffer memory organization and is fully non-blocking. It can support a total aggregate throughput of 9.6 Gb/s, organized in any combination of up to 32 155 Mb/s, eight 622 Mb/s, or four 1.2 Gb/s full-duplex links. The switch can be fabricated on a single chip, and includes an internal 4 MB memory buffer capable of storing over 85,000 cells. When combined with external support circuitry, the switch is competitive with commercial offerings in its feature set, and significantly less expensive than existing solutions. The switch is targeted to WAN infrastructure applications such as wide-area Internet access, data back bones, and digital telephony, where we feel untapped markets exist, but it is also usable for ATM-based LANs and even could be modified to penetrate the potentially lucrative Fast and Gigabit Ethernet marketsen
Type of ItemΠλήρης Δημοσίευση σε Συνέδριοel
Type of ItemConference Full Paperen
Licensehttp://creativecommons.org/licenses/by/4.0/en
Date of Item2015-11-16-
Date of Publication1999-
Bibliographic CitationI. Papaefstathiou, A. Brown, J. Simer, D. Sobel, J. Sutaria, Y. WangT. Blackwell, M. Smith, W. Yang, "An IRAM-based architecture for a single-chip ATM switch," in 6th IEEE International Conference on Electronics, Circuits and Systems, 1999, pp. 97 - 100. doi: 10.1109/ICECS.1999.812232en

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