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Using MML to simulate multiple dual-ported SRAMs: Parallel routing lookups in an ATM switch controller

Papaefstathiou Ioannis, Brown A., Chian D., Mehta N., Simer J., Blackwell T., Smith M., Yang W.

Πλήρης Εγγραφή

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Περίληψη

The need for fast parallel table lookups is evident in many modern hardware applications, such as network switches, hard disk controllers, and encryption devices. Typically, most of these table lookups are performed in fast and expensive on-board SRAMs in order to reduce latency. These SRAMs frequently provide dual-ported access at speeds of up to 20 ns. However, for applications demanding many large look-up tables, SRAM's physical size, density, power requirements, and cost are prohibitive. In this paper, we address this problem through one particularly demanding example: the routing control in a sophisticated ATM switch. We present a design that uses merged memory and logic (MML, a modified form of DRAM) to simulate dual-ported SRAM in performing tens of table lookups in parallel. Our solution fits on one chip instead of over 300 required by an existing design, providing an integrated, low-power solution while still meeting the rigorous timing constraints of the application.

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