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Big data processing with FPGA supercomputers: opportunities and challenges

Dollas Apostolos

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URIhttp://purl.tuc.gr/dl/dias/0CE1F058-9DAD-489A-B5D8-5DAB3D00602D-
Identifierhttps://doi.org/10.1109/ISVLSI.2014.65-
Identifierhttp://ieeexplore.ieee.org/abstract/document/6903409/-
Languageen-
Extent6 pagesen
TitleBig data processing with FPGA supercomputers: opportunities and challengesen
CreatorDollas Apostolosen
CreatorΔολλας Αποστολοςel
PublisherInstitute of Electrical and Electronics Engineersen
Content SummaryThe use of Field Programmable Gate Arrays (FPGAs) as high-end compute engines has proven to be successful in several classes of problems and their application as "big data" supercomputers has already started to be investigated. This paper presents the main approaches in the sate-of-the-art with research highlights as well as skeptics considerations. It will then proceed to analyze the storage vs. network characteristics of present-day systems in the context of "big data" processing. The analysis will reveal that there exist obstacles to overcome in virtually all present-day FPGA supercomputers. This work will then proceed with proposed approaches from on-going research in the AFORMI project. These are the decoupling of the memory data accesses from execution, leading to transaction oriented compute paradigms, the use of FPGAs as "snooping" processors, and the need for low-overhead FPGA interconnection protocols.en
Type of ItemΔημοσίευση σε Συνέδριοel
Type of ItemConference Publicationen
Licensehttp://creativecommons.org/licenses/by/4.0/en
Date of Item2015-11-17-
Date of Publication2014-
SubjectArchitecture, Softwareen
SubjectComputer software--Architectureen
SubjectComputer software--Designen
SubjectComputer software architectureen
Subjectsoftware architectureen
Subjectarchitecture softwareen
Subjectcomputer software architectureen
Subjectcomputer software designen
Bibliographic CitationA. Dollas, "Big data processing with FPGA supercomputers: opportunities and challenges," in IEEE Computer Society Annual Symposium on VLSI, 2014, pp. 474-479. doi:10.1109/ISVLSI.2014.65en

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