Institutional Repository
Technical University of Crete
EN  |  EL

Search

Browse

My Space

Hardware-software codesign and parallel implementation of a golomb ruler derivation engine

Sotiriadis Evripidis, Dollas Apostolos, Athanas Peter

Full record


URI: http://purl.tuc.gr/dl/dias/D210CF70-0509-4012-84A9-69A85C2621C3
Year 2000
Type of Item Conference Publication
License
Details
Bibliographic Citation E. Sotiriades, A. Dollas and P. Athanas, "Hardware-software codesign and parallel implementation of a golomb ruler derivation engine," in 8th International IEEE Symposium on Field-Programmable Custom Computing Machines, 2000, pp. 227-235. doi: 10.1109/FPGA.2000.903410 https://doi.org/10.1109/FPGA.2000.903410
Appears in Collections

Summary

A new architecture for Golomb ruler derivation has been developed so that rulers up to 24 marks can be proven on it. In this architecture, 8-mark stubs that are derived on a personal computer are subsequently processed by the FCCM, called GE2, allowing for parallel processing of as many stubs as are the available FPGAs. Actual runs of the new design have been performed on the TOP parallel FPGA machine at Virginia Tech. This paper presents the design improvements over the original architecture, which include single FPGA implementation, hardware/software codesign, FIFO based I/O, design for parallel execution, and performance results from actual runs.

Services

Statistics