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Hardware-software codesign and parallel implementation of a golomb ruler derivation engine

Sotiriadis Evripidis, Dollas Apostolos, Athanas Peter

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URIhttp://purl.tuc.gr/dl/dias/D210CF70-0509-4012-84A9-69A85C2621C3-
Identifierhttp://ieeexplore.ieee.org/document/903410/-
Identifierhttps://doi.org/10.1109/FPGA.2000.903410-
Languageen-
Extent9 pagesen
TitleHardware-software codesign and parallel implementation of a golomb ruler derivation engineen
CreatorSotiriadis Evripidisen
CreatorΣωτηριαδης Ευριπιδηςel
CreatorDollas Apostolosen
CreatorΔολλας Αποστολοςel
CreatorAthanas Peteren
PublisherInstitute of Electrical and Electronics Engineersen
Content SummaryA new architecture for Golomb ruler derivation has been developed so that rulers up to 24 marks can be proven on it. In this architecture, 8-mark stubs that are derived on a personal computer are subsequently processed by the FCCM, called GE2, allowing for parallel processing of as many stubs as are the available FPGAs. Actual runs of the new design have been performed on the TOP parallel FPGA machine at Virginia Tech. This paper presents the design improvements over the original architecture, which include single FPGA implementation, hardware/software codesign, FIFO based I/O, design for parallel execution, and performance results from actual runs.en
Type of ItemΔημοσίευση σε Συνέδριοel
Type of ItemConference Publicationen
Licensehttp://creativecommons.org/licenses/by/4.0/en
Date of Item2015-11-17-
Date of Publication2000-
SubjectComputers--Programmingen
SubjectElectronic computer programmingen
SubjectElectronic data processing--Programmingen
SubjectElectronic digital computers--Programmingen
SubjectProgramming (Electronic computers)en
Subjectcomputer programmingen
Subjectcomputers programmingen
Subjectelectronic computer programmingen
Subjectelectronic data processing programmingen
Subjectelectronic digital computers programmingen
Subjectprogramming electronic computersen
Bibliographic CitationE. Sotiriades, A. Dollas and P. Athanas, "Hardware-software codesign and parallel implementation of a golomb ruler derivation engine," in 8th International IEEE Symposium on Field-Programmable Custom Computing Machines, 2000, pp. 227-235. doi: 10.1109/FPGA.2000.903410en

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