Ιδρυματικό Αποθετήριο
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Πολυτεχνείο Κρήτης
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| URI | http://purl.tuc.gr/dl/dias/EC27247D-2AC7-4A10-B2F4-83029355F5A1 | - |
| Αναγνωριστικό | https://doi.org/10.1109/FPT.2010.5681461 | - |
| Αναγνωριστικό | http://ieeexplore.ieee.org/document/5681461/ | - |
| Γλώσσα | en | - |
| Μέγεθος | 4 pages | en |
| Τίτλος | GE3: A single FPGA client-server architecture for golomb ruler derivation | en |
| Δημιουργός | Malakonakis Pavlos | en |
| Δημιουργός | Μαλακωνακης Παυλος | el |
| Δημιουργός | Sotiriadis Evripidis | en |
| Δημιουργός | Σωτηριαδης Ευριπιδης | el |
| Δημιουργός | Dollas Apostolos | en |
| Δημιουργός | Δολλας Αποστολος | el |
| Εκδότης | Institute of Electrical and Electronics Engineers | en |
| Περίληψη | Optimal Golomb Rulers (OGR) are a discrete mathematics problem for which there is no known closed form solution. This problem is so computationally intensive that it is considered a “grand challenge problem”. Since the early 1990's FPGA-based OGR engines have been designed, with excellent performance vs. general-purpose computing. This paper presents a new, single FPGA clientserver architecture for OGR derivation. The new client architecture supports parallel evaluation of multiple hypotheses (up to 16), each implemented as a shift operation, and one server which can support many clients. The new architecture has a measured speedup of 8 against an Intel Core 2 Duo processor for a single client supporting up to eight “shifts” and running on a Virtex 2P FPGA, and a post place-and-route simulation-derived speedup of 160 with four clients on a Virtex 5 FPGA, each supporting up to sixteen “shifts”. The new architecture has been fully implemented and runs on actual hardware, whereas simulations have been used to project performance on FPGA's which were not available for experimentation. | en |
| Τύπος | Δημοσίευση σε Συνέδριο | el |
| Τύπος | Conference Publication | en |
| Άδεια Χρήσης | http://creativecommons.org/licenses/by/4.0/ | en |
| Ημερομηνία | 2015-11-17 | - |
| Ημερομηνία Δημοσίευσης | 2010 | - |
| Θεματική Κατηγορία | Field programmable logic arrays | en |
| Θεματική Κατηγορία | FPGAs | en |
| Θεματική Κατηγορία | field programmable gate arrays | en |
| Θεματική Κατηγορία | field programmable logic arrays | en |
| Θεματική Κατηγορία | fpgas | en |
| Βιβλιογραφική Αναφορά | P. Malakonakis, E. Sotiriades and A. Dollas, "GE3: A single FPGA client-server architecture for golomb ruler derivation," in International Conference on Field-Programmable Technology, 2010, pp. 470-473. doi: 10.1109/FPT.2010.5681461 | en |
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