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Exploring FPGAs for accelerating the phylogenetic likelihood function

Alachiotis, Nikolaos, Sotiriadis Evripidis, Dollas Apostolos, Stamatakis Alexandros

Απλή Εγγραφή


URIhttp://purl.tuc.gr/dl/dias/FC0A7BDD-AC15-4826-B4BD-63485692032D-
Αναγνωριστικόhttps://doi.org/10.1109/IPDPS.2009.5160929-
Αναγνωριστικόhttp://ieeexplore.ieee.org/abstract/document/5160929/-
Γλώσσαen-
Μέγεθος8 pagesen
ΤίτλοςExploring FPGAs for accelerating the phylogenetic likelihood functionen
ΔημιουργόςAlachiotis, Nikolaosen
ΔημιουργόςSotiriadis Evripidisen
ΔημιουργόςΣωτηριαδης Ευριπιδηςel
ΔημιουργόςDollas Apostolosen
ΔημιουργόςΔολλας Αποστολοςel
ΔημιουργόςStamatakis Alexandrosen
ΔημιουργόςΣταματακης Αλεξανδροςel
ΕκδότηςInstitute of Electrical and Electronics Engineersen
ΠερίληψηDriven by novel biological wet lab techniques such as pyrosequencing there has been an unprecedented molecular data explosion. The growth of biological sequence data has significantly out-paced Moore's law. This development also poses new computational and architectural challenges for the field of phylogenetic inference, i.e., the reconstruction of evolutionary histories (trees) for a set of organisms which are represented by respective molecular sequences. Phylogenetic trees are currently increasingly reconstructed from multiple genes or even whole genomes. The introduced term "phylogenomics" reflects this development. Hence, there is an urgent need to deploy and develop new techniques and computational solutions to calculate the computationally intensive scoring functions for phylogenetic trees. In this paper, we propose a dedicated computer architecture to compute the phylogenetic maximum likelihood (ML) function. The ML criterion represents one of the most accurate statistical models for phylogenetic inference and accounts for 85% to 95% of total execution time in all state-of-the-art ML-based phylogenetic inference programs. We present the implementation of our architecture on an FPGA (field programmable gate array) and compare the performance to an efficient C implementation of the ML function on a high-end multi-core architecture with 16 cores. Our results are two-fold: (i) the initial exploratory implementation of the ML function for trees comprising 4 up to 512 sequences on an FPGA yields speedups of a factor 8.3 on average compared to execution on a single-core and is faster than the OpenMP-based parallel implementation on up to 16 cores in all but one case; and (ii) we are able to show that current FPGAs are capable to efficiently execute floating point intensive computational kernels.en
ΤύποςΔημοσίευση σε Συνέδριοel
ΤύποςConference Publicationen
Άδεια Χρήσηςhttp://creativecommons.org/licenses/by/4.0/en
Ημερομηνία2015-11-17-
Ημερομηνία Δημοσίευσης2009-
Θεματική ΚατηγορίαAutomatic computersen
Θεματική ΚατηγορίαAutomatic data processorsen
Θεματική ΚατηγορίαComputer hardwareen
Θεματική ΚατηγορίαComputing machines (Computers)en
Θεματική ΚατηγορίαElectronic brainsen
Θεματική ΚατηγορίαElectronic calculating-machinesen
Θεματική ΚατηγορίαElectronic computersen
Θεματική ΚατηγορίαHardware, Computeren
Θεματική Κατηγορίαcomputersen
Θεματική Κατηγορίαautomatic computersen
Θεματική Κατηγορίαautomatic data processorsen
Θεματική Κατηγορίαcomputer hardwareen
Θεματική Κατηγορίαcomputing machines computersen
Θεματική Κατηγορίαelectronic brainsen
Θεματική Κατηγορίαelectronic calculating machinesen
Θεματική Κατηγορίαelectronic computersen
Θεματική Κατηγορίαhardware computeren
Βιβλιογραφική ΑναφοράN. Alachiotis, E. Sotiriades, A. Dollas and A. Stamatakis, "Exploring FPGAs for accelerating the phylogenetic likelihood function," in IEEE International Symposium on Parallel & Distributed Processing, 2009, pp. 1-8. doi: 10.1109/IPDPS.2009.5160929en

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