Ιδρυματικό Αποθετήριο
Πολυτεχνείο Κρήτης
Πολυτεχνείο Κρήτης
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| URI: | http://purl.tuc.gr/dl/dias/84EBD8AD-9090-4A3F-901E-6C4C5A6D7DBF | ||
| Έτος | 2009 | ||
| Τύπος | Δημοσίευση σε Συνέδριο | ||
| Άδεια Χρήσης |
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| Βιβλιογραφική Αναφορά | P. Malakonakis, M. Smerdis, E. Sotiriades and A. Dollas, "An FPGA-based Sudoku Solver based on Simulated Annealing methods," in International Conference on Field-Programmable Technology, 2009, pp. 522-525. doi: 10.1109/FPT.2009.5377608 https://doi.org/10.1109/FPT.2009.5377608 | ||
| Εμφανίζεται στις Συλλογές |
The Sudoku simulated annealing solver -SSAS is a probabilistic Sudoku solver. The general design is capable of solving a Sudoku board of order up to fifteen (15 Ã 15 Ã 15 Ã 15). It has been designed and fully implemented on a Xilinx Virtex II Pro - based Digilent XUP board. The solver has a serial-port interface to download problems and upload results to a personal computer, according to the specifications of the relevant competition of the 2009 International Conference on Field Programmable Technology (FPT). The SSAS has solved in actual hardware Sudoku puzzles of up to order 12 within the competition-imposed time limits.
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