URI | http://purl.tuc.gr/dl/dias/84EBD8AD-9090-4A3F-901E-6C4C5A6D7DBF | - |
Identifier | https://doi.org/10.1109/FPT.2009.5377608 | - |
Identifier | http://ieeexplore.ieee.org/document/5377608/?reload=true&arnumber=5377608 | - |
Language | en | - |
Extent | 4 pages | en |
Title | An FPGA-based sudoku solver based on simulated annealing methods | en |
Creator | Malakonakis Pavlos | en |
Creator | Μαλακωνακης Παυλος | el |
Creator | Smerdis Miltiadis | en |
Creator | Σμερδης Μιλτιαδης | el |
Creator | Sotiriadis Evripidis | en |
Creator | Σωτηριαδης Ευριπιδης | el |
Creator | Dollas Apostolos | en |
Creator | Δολλας Αποστολος | el |
Publisher | Institute of Electrical and Electronics Engineers | en |
Content Summary | The Sudoku simulated annealing solver -SSAS is a probabilistic Sudoku solver. The general design is capable of solving a Sudoku board of order up to fifteen (15 Ã 15 Ã 15 Ã 15). It has been designed and fully implemented on a Xilinx Virtex II Pro - based Digilent XUP board. The solver has a serial-port interface to download problems and upload results to a personal computer, according to the specifications of the relevant competition of the 2009 International Conference on Field Programmable Technology (FPT). The SSAS has solved in actual hardware Sudoku puzzles of up to order 12 within the competition-imposed time limits. | en |
Type of Item | Δημοσίευση σε Συνέδριο | el |
Type of Item | Conference Publication | en |
License | http://creativecommons.org/licenses/by/4.0/ | en |
Date of Item | 2015-11-17 | - |
Date of Publication | 2009 | - |
Subject | Field programmable logic arrays | en |
Subject | FPGAs | en |
Subject | field programmable gate arrays | en |
Subject | field programmable logic arrays | en |
Subject | fpgas | en |
Bibliographic Citation | P. Malakonakis, M. Smerdis, E. Sotiriades and A. Dollas, "An FPGA-based Sudoku Solver based on Simulated Annealing methods," in International Conference on Field-Programmable Technology, 2009, pp. 522-525. doi: 10.1109/FPT.2009.5377608 | en |