Institutional Repository
Technical University of Crete
Technical University of Crete
EN
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EL
| URI | http://purl.tuc.gr/dl/dias/6A2C4F40-98E1-4C6E-BA21-E0D37A076DFC | - |
| Identifier | https://doi.org/10.26233/heallink.tuc.62753 | - |
| Language | en | - |
| Extent | 93 pages | en |
| Title | Α user-transparent system for virtualizing reconfigurable hardware accelerators | en |
| Title | Ένα διαφανές προς το χρήστη σύστημα για την υποστήριξη εικονικών επιταχυντών αναδιατασσόμενου υλικού | el |
| Creator | Vatsolakis Charalabos | en |
| Creator | Βατσολακης Χαραλαμπος | el |
| Contributor [Thesis Supervisor] | Pnevmatikatos Dionysios | en |
| Contributor [Thesis Supervisor] | Πνευματικατος Διονυσιος | el |
| Contributor [Committee Member] | Dollas Apostolos | en |
| Contributor [Committee Member] | Δολλας Αποστολος | el |
| Contributor [Committee Member] | Papaefstathiou Ioannis | en |
| Contributor [Committee Member] | Παπαευσταθιου Ιωαννης | el |
| Publisher | Πολυτεχνείο Κρήτης | el |
| Publisher | Technical University of Crete | en |
| Academic Unit | Technical University of Crete::School of Electronic and Computer Engineering | en |
| Academic Unit | Πολυτεχνείο Κρήτης::Σχολή Ηλεκτρονικών Μηχανικών και Μηχανικών Υπολογιστών | el |
| Content Summary | Hardware based acceleration is highly efficient, but there are several factors limiting its adoption. The most notable of those, is the lack of a standardized system, capable of providing a transparent interface between software and reconfigurable hardware. The product of this work, is a system capable of loading acceletors and perform I/Os in a completely transparent to the user manner. The user is capable of implementing an accelerator compatible to the system by using a standard set of ports. The access to this accelerator is aided by a given software API. The system is based on the PCI Express interface (version 1, 4 lanes) for data transactions and the ICAP for reconfiguration. There are three partially reconfigurable regions available, while the systems software is responsible for scheduling the accelerators waiting for execution. There are four scheduling policies implemented; noop, simple, out of order, and forced. The first two, take in account the submission order, while the others, target to reduce the number of reconfigurations. The total throughput our system reached, equals 618 MB/s for transmissions, 544 MB/s for receptions and 488 MB/s for reconfigurations. The behaviour of our system under heavy load, was evaluated through an edge detection system consisting of four accelerators running sequentially. We sustained a real-time throughput of 30 FPS in 720p HD datasets, even when the least efficient scheduling policy was selected. | en |
| Type of Item | Μεταπτυχιακή Διατριβή | el |
| Type of Item | Master Thesis | en |
| License | http://creativecommons.org/licenses/by-nc/4.0/ | en |
| Date of Item | 2016-01-28 | - |
| Date of Publication | 2015 | - |
| Subject | Computer architecture | en |
| Bibliographic Citation | Charalabos Vatsolakis, "Α user-transparent system for virtualizing reconfigurable hardware accelerators", Master Thesis, School of Electronic and Computer Engineering, Technical University of Crete, Chania, Greece, 2015 | el |
| Bibliographic Citation | Χαράλαμπος Βατσολάκης, "Ένα διαφανές προς το χρήστη σύστημα για την υποστήριξη εικονικών επιταχυντών αναδιατασσόμενου υλικού", Μεταπτυχιακή Διατριβή, Σχολή Ηλεκτρονικών Μηχανικών και Μηχανικών Υπολογιστών, Πολυτεχνείο Κρήτης, Χανιά, Ελλάς, 2015 | el |
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