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 946-960 out of 3115 results
946 I. Papaefstathiou, C. Sotiriou. (2002,May). Read, Use, Simulate, Experiment and Build : An Integrated Approach for Teaching Computer Architecture. Presented at 8th Workshop on Computer Architecture Education (WCAE 2002), 29th International Symposium on Computer Architecture (ISCA 2002). [Online]. Available: https://www.ncsu.edu/wcae/ISCA2002/submissions/papaefstathiou.pdf2015-11-16
947 I. Papaefstathiou, "An ultra high-speed compressor for packet networks," in 8th IEEE International Conference on Electronics, Circuits and Systems, 2001, pp. 1259 - 1263. doi: 10.1109/ICECS.2001.9574442015-11-16
948 I. Papaefstathiou, "Measurement Based Connection Admission Control Algorithm for ATM Networks that Use Low Level Compression," in 7th International Conference on Intelligence in Services and Networks, ISandN 2000, pp. 49-60. doi: 10.1007/3-540-46525-1_42015-11-16
949 G. Kornaros, I. Papaefstathiou, "An Innovative Resource Management Scheme for Multi-gigabit Networking Systems," in 6th IEEE International Conference on High Speed Networks and Multimedia Communications, 2003, pp. 165-175. doi: 10.1007/978-3-540-45076-4_172015-11-16
950 T. Orphanoudakis, I. Papaefstathiou, G. Komaros, "Active flow identifiers for scalable, QoS scheduling in 10-Gbps network processors," in Proceedings of the 2003 International Symposium on Circuits and Systems, pp. II-97 - II-100 . doi: 10.1109/ISCAS.2003.12059012015-11-16
951 C. Sotiriou, I. Papaefstathiou, "A Design-Space Exploration of Alternative DES Implementations," presented at 10th IEEE International Conference on Electronics, Circuits and Systems, Sharja, U.A.E., 2003.2015-11-16
952 I. Papaefstathiou, "Titan II: an IPComp processor for 10Gbit/sec networks," in IEEE Computer Society Annual Symposium on VLSI, 2003, pp. 234 - 235. doi: 10.1109/ISVLSI.2003.11834792015-11-16
953 M. Katevenis, G. Passas, D. Simos, I. Papaefstathiou and N. Chrysos, "Variable packet size buffered crossbar (CICQ) switches," presented at IEEE International Conference on Communications, Paris, France, 2004.2015-11-16
954 I. Papaefstathiou, D. Pnevmatikatos, V. Dimopoulos, "A Memory-Efficient Reconfigurable Aho-Corasick FSM Implementation for Intrusion Detection Systems," in International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, 2007, pp. 186 - 193. doi: 10.1109/ICSAMOS.2007.42857502015-11-16
955 I. Papaefstathiou, V. Papaefstathiou, "Memory-Efficient 5D Packet Classification At 40 Gbps," in 26th IEEE International Conference on Computer Communications2007, pp. 1370 - 1378. doi: 10.1109/INFCOM.2007.1622015-11-16
956 G. Kornaros I. Papaefstathiou D. Pnevmatikatos, "Dynamic Software-Assisted Monitoring of On-Chip Interconnects," presented at Workshop on Diagnostic Services in Network-on-Chips, IEEEDesign Automation and Test in Europe, Nice, France, 2007.2015-11-16
957 I. Papaefstathiou, V. Papaefstathiou, "A Hardware-Engine for Layer-2 classification in low-storage, ultra high bandwidth environments," in Proceedings Design, Automation and Test in Europe, 2006, pp. 1 - 6. doi: 10.1109/DATE.2006.2438132015-11-16
958 V. Papaefstathiou, I. Papaefstathiou, "An innovative low-cost Classification Scheme for combined multi-Gigabit IP and Ethernet Networks," in IEEE International Conference on Communications, 2006, pp. 211 - 216. doi: 10.1109/ICC.2006.2547292015-11-16
959 V. Papaefstathiou, I. Papaefstathiou. (2005,November). A Memory Efficient, 100 Gb/sec MAC Classification Engine . Presented at 30th Annual IEEE Conference on Local Computer Networks (LCN). [Online]. Available: http://lens.csie.ncku.edu.tw/Library/Paper/IEEE%20LCN%202005/lcn057.pdf2015-11-16
960 T. Otphanoudakis, G. Kornaros, C. Kachris, I. Mavroidis, A. Nikologiannis, I. Papaefstathiou, "Queue management in network processors," in Proceedings Design, Automation and Test in Europe, 2005, pp. 112 - 117. doi: 10.1109/DATE.2005.2512015-11-16
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