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Parallel architecture for the Scalejoin algorithm implementation on the Convey supercomputer

Karandeinos Ektor

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Year 2017
Type of Item Diploma Work
Bibliographic Citation Ektor Karandeinos, "Parallel architecture for the Scalejoin algorithm implementation on the Convey supercomputer", Diploma Work, School of Electrical and Computer Engineering, Technical University of Crete, Chania, Greece, 2017
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Stream join consists one of the most resource-intensive operators in stream processing. Due to this characteristic, a big interest has been created in building high throughput and low latency systems which will be able to process real-time, bursty and rate varying data streams. This thesis proposes an FPGA-based architecture which is based on one of the most efficient stream join algorithms, i.e ScaleJoin. The proposed architecture extends the first hardware-based architecture of the ScaleJoin algorithm. The first hardware implementation achieves high throughput and scalability but suffers from low resources utilization. In this thesis, we propose a novel architecture to achieve greater level of parallelism and exploit the available resources. Our system runs on Convey HC-2ex hybrid computer equipped with two six-core Intel Xeon E5-2640 processors running at 2.5 GHz and four Virtex 6 LX760 FPGAs. The experimental performance evaluation shows that our system totally outperforms the corresponding software-based solution and improves greatly the performance of the first hardware implementation.

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