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Technical University of Crete
Technical University of Crete
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| URI | http://purl.tuc.gr/dl/dias/40BA5708-F048-4D3F-9D4B-1E86417AAB1D | - |
| Identifier | https://doi.org/10.1145/b3229631.3229635 | - |
| Identifier | https://dl.acm.org/citation.cfm?id=3229635 | - |
| Language | en | - |
| Extent | 10 pages | en |
| Title | A performance evaluation of multi-FPGA architectures for computations of information transfer | en |
| Creator | Iordanou Konstantinos | en |
| Creator | Ιορδανου Κωνσταντινος | el |
| Creator | Nikolakaki Sofia-Maria | en |
| Creator | Νικολακακη Σοφια-Μαρια | el |
| Creator | Malakonakis Pavlos | en |
| Creator | Μαλακωνακης Παυλος | el |
| Creator | Dollas Apostolos | en |
| Creator | Δολλας Αποστολος | el |
| Publisher | Association for Computing Machinery | en |
| Content Summary | Mutual Information (MI) and Transfer Entropy (TE) algorithms compute statistical measurements on the information shared between two dependent random processes. These measurements have focused on pairwise computations of time series in a broad range of fields, such as Econometrics, Neuroscience, Data Mining and Computer Vision. Unlike previous works which mostly focus on 8-bit Computer Vision applications, this work proposes the first generic hardware architectures for the acceleration of the MI and TE algorithms to target any dataset for a realistic, multi-FPGA platform. We evaluate and compare two such systems, the Maxeler MAX3A Vectis and the Convey HC-2ex platforms, and provide insight into each one's benefits and limitations. All reported results are from actual experimental runs, including I/O overhead, and comprise lower bounds of our systems' full capabilities for large-scale datasets. These are compared to equivalent optimized multi-threaded software implementations, yielding ∼19x speedup vs. out-of-the-box software packages and ∼2.5x speedup vs. highly optimized software that is presented in the related work. These hardware architectures are obtained with a small fraction of the FPGA resources, and are limited by I/O bandwidth. This means that with near-future FPGA I/O capabilities, the performance of the architectures presented in this work for the O(n 2 ) Mutual Information and the O(n 3 ) Transfer Entropy problems will easily scale up. | en |
| Type of Item | Πλήρης Δημοσίευση σε Συνέδριο | el |
| Type of Item | Conference Full Paper | en |
| License | http://creativecommons.org/licenses/by/4.0/ | en |
| Date of Item | 2019-08-29 | - |
| Date of Publication | 2018 | - |
| Subject | Convey | en |
| Subject | Hardware | en |
| Subject | Maxeler | en |
| Subject | Multi-FPGA | en |
| Subject | Mutual information | en |
| Subject | Transfer entropy | en |
| Bibliographic Citation | K. Iordanou, S. M. Nikolakaki, P. Malakonakis and A. Dollas, "A performance evaluation of multi-FPGA architectures for computations of information transfer," in 18th International Conference on Embedded Computer Systems: Architectures, MOdeling and Simulation, 2018, pp. 1-9. doi: 10.1145/b3229631.3229635 | en |
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