URI | http://purl.tuc.gr/dl/dias/3E0F8C3A-1AEC-4744-BFC1-51E75746F36E | - |
Identifier | https://doi.org/10.1109/TED.2018.2838101 | - |
Identifier | https://ieeexplore.ieee.org/document/8371530 | - |
Language | en | - |
Extent | 7 pages | en |
Title | Charge-based modeling of long-channel symmetric double-gate junction FETs-Part I: drain current and transconductances | en |
Creator | Makris Nikolaos | en |
Creator | Μακρης Νικολαος | el |
Creator | Jazaeri, Farzan 1984- | en |
Creator | Sallese, Jean-Michel 1964- | en |
Creator | Sharma Rupendra Kumar | en |
Creator | Bucher Matthias | en |
Creator | Bucher Matthias | el |
Publisher | Institute of Electrical and Electronics Engineers | en |
Content Summary | The double-gate (DG) junction field-effect transistor (JFET) is a classical electron device, with a simple structure that presents many advantages in terms of not only device fabrication but also its operation. The device has been largely used in low-noise applications, but also more recently, in power electronics. Physics-based compact models for JFETs, contrary to MOSFETs, are, however, scarce. In this paper, an analytical, charge-based model is established for the mobile charges, drain current, and transconductances of symmetric DG JFETs, covering all regions of device operation. The model is unified and continuous from subthreshold to linear and saturation operation and is valid over a large temperature range. This charge-based model constitutes the basis of a full compact model of the DG JFET. | en |
Type of Item | Peer-Reviewed Journal Publication | en |
Type of Item | Δημοσίευση σε Περιοδικό με Κριτές | el |
License | http://creativecommons.org/licenses/by/4.0/ | en |
Date of Item | 2019-09-03 | - |
Date of Publication | 2018 | - |
Subject | Analytical model | en |
Subject | Circuit simulation | en |
Subject | Compact model | en |
Subject | JFET | en |
Subject | Junction field-effect transistor | en |
Subject | Temperature effect | en |
Bibliographic Citation | N. Makris, F. Jazaeri, J.-M. Sallese, R.K. Sharma and M. Bucher, "Charge-based modeling of long-channel symmetric double-gate junction FETs-Part I: drain current and transconductances," IEEE Trans. Electron Devices, vol. 65, no. 7, pp. 2744-2750, Jul. 2018. doi: 10.1109/TED.2018.2838101 | en |