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Design and implementation of hardware architectures for pricing financial derivatives on reconfigurable logic

Miteloudi Konstantina

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Summary

Option pricing is a fundamental problem in financial sector. This work presents a hardware accelerator on FPGAs for Option Pricing using Crank-Nicolson Finite Difference scheme for solving the Black-Scholes PDE. A variant of Cyclic Reduction called normalized Cyclic Reduction algorithm is used as Tridiagonal Solver. The thesis contains all the theoretical background of option pricing models and finite difference schemes. A literature review had been carried out covering extensively all the FPGA based option pricing accelerators. The effort of this work was concentrated mainly to hardware low-level optimizations that were implemented to produce a parallel system that scale up efficiently. These optimizations, such as custom precision arithmetic, fused operators, pipelined designs etc., were on level of hardware design and had scope to produce a highly parallel hardware architecture. Three different hardware architectures for the main computation core were presented. First a naïve non-pipelined at 32bit precision, next a pipelined architecture using a custom 3 operand adder, also at 32bit precision and finally the proposed hardware architecture with a Fused Multiply Addition operator (FMA or fmadd). This architecture was implemented with 48bit precision, which was selected after taking into account error analysis with MPRF library and design decisions. The implementation was on a Xilinx FPGA device, Ultrascale xcvu9p, and achieved clock frequency 263MHZ.

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