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Extending a 65nm CMOS process design kit for high total ionizing dose effects

Nikolaou Aristeidis, Bucher Matthias, Makris Nikolaos, Papadopoulou Alexia, Chevas Loukas, Borghello Giulio, Koch Henri D., Kloukinas Kostas C., Poikela Tuomas S., Faccio Federico

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Year 2018
Type of Item Conference Full Paper
Bibliographic Citation A. Nikolaou, M. Bucher, N. Makris, A. Papadopoulou, L. Chevas, G. Borghello, H.D. Koch, K. Kloukinas, T.S. Poikela and F. Faccio, "Extending a 65nm CMOS process design kit for high total ionizing dose effects," in 7th International Conference on Modern Circuits and Systems Technologies, 2018, pp. 1-4. doi: 10.1109/MOCAST.2018.8376561
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Standard CMOS Process Design Kits (PDKs) do not address degradation the technology incurs when exposed to high Total Ionizing Dose (TID). Front-end electronics for the High-Luminosity Large Hadron Collider are expected to be exposed up to ten-fold doses. Bulk CMOS at 65 nm is a strong contender for such electronics due to a favorable trade-off among cost, performance, and TID-sensitivity. The present paper presents the extension of a foundry-provided PDK to cover also high TID effects. TID experiments have been carried out up to 500 Mrad. The PDK is based on binned BSIM4 models, which are adapted to different TID levels. Hence, designers may choose among different TID levels for their designs, contributing importantly to radiation-hard design practice.