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Technical University of Crete
Technical University of Crete
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| URI: | http://purl.tuc.gr/dl/dias/BDACB96B-6671-4C6A-B365-16D606E40F10 | ||
| Year | 2018 | ||
| Type of Item | Conference Full Paper | ||
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| Bibliographic Citation | F. Kostarelos, G. Charitopoulos and D.N. Pnevmatikatos, "Less is more: increasing the scope of hardware debugging with compression," in 4th Panhellenic Conference on Electronics and Telecommunications, 2018, pp. 1-4. doi: 10.1109/PACET.2017.8259958 https://doi.org/10.1109/PACET.2017.8259958 | ||
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In this work we consider the slow and tedious phase of hardware debugging in FPGAs. The process of hardware debugging is normally done via Internal Logic Analyzer (ILA) circuits, which add user observability in internal FPGA signals. The user first defines the target for debugging signal and a triggering condition. Then the ILA stores traces of it in trace buffers, these traces are finally transferred to a host PC for the user to observe. The user also has to consider the limited FPGA memory resources, which result in small-sized trace buffers, an important restriction of hardware debugging. In this paper, we attempt to increase the scope of hardware tracing, i.e. the number of samples written on the trace buffers, with the use of compression. We use the LZW algorithm and find that we can increase the debugging signals number of recorded samples by 90%, i.e. have double the amount of useful data with the same memory usage. On the memory plane we conclude that, for the same number of recorded samples, our architecture uses less than half the resources compared to the standard Xilinx ILA block for signal tracing.
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